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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM 32-bit Byte-Write       ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Tadej Markovic, tadej.markovic@gmail.com              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// New 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_32_bw
  (
`ifdef OR1200_BIST
   // RAM BIST
   mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
   // Generic synchronous single-port RAM interface
   clk, rst, ce, we, addr, di, doq
`ifdef OR1200_RAM_PARITY
   , p_err
`endif   
   );
 
   //
   // Default address and data buses width
   //
   parameter aw = 10;
   parameter dw = 32;
 
   parameter bw = 8;
 
 
`ifdef OR1200_BIST
   //
   // RAM BIST
   //
   input mbist_si_i;
   input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
   output 				  mbist_so_o;
`endif
 
`ifdef OR1200_RAM_PARITY
   output 				  p_err; // parity error indicator
`endif
 
   //
   // Generic synchronous single-port byte-writable RAM interface
   //
   input 				  clk;	// Clock
   input 				  rst;  // Reset
   input 				  ce;	// Chip enable input
   input [3:0]				  we;	// Write enable input
   input [aw-1:0] 			  addr;	// address bus inputs
   input [dw-1:0] 			  di;	// input data bus
   output [dw-1:0] 			  doq;	// output data bus
 
 
   //
   // Internal wires and registers
   //
 
   //
   // Generic single-port synchronous RAM model
   //
 
   //
   // Generic RAM's registers and wires
   //
`ifdef OR1200_RAM_PARITY
   reg [bw:0] 	mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [bw:0] 	mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [bw:0] 	mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [bw:0] 	mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
   reg [bw-1:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [bw-1:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [bw-1:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [bw-1:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`endif
   reg [aw-1:0] addr_reg;		// RAM address register
 
`ifdef OR1200_RAM_PARITY
   wire [(dw+(dw/8))-1:0] 		  doq_wire;
   wire [bw:0] 				  doq0_wire;
   wire [bw:0] 				  doq1_wire;
   wire [bw:0] 				  doq2_wire;
   wire [bw:0] 				  doq3_wire;
   wire [(dw/8)-1:0] 			  di_p;
   wire [(dw/8)-1:0] 			  do_p;
   wire [(dw/8)-1:0] 			  parity_err;
   reg 					  ce_r;   
`else
   wire [dw-1:0] 			  doq_wire;
`endif
 
`ifdef OR1200_RAM_PARITY
   genvar 			i;
   generate
      for (i=0;i<(dw/8);i=i+1) begin: paritygen
	 or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
	 or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]), 
				.p_i(do_p[i]), .err_o(parity_err[i]));
      end
   endgenerate
 
   // Extract parity bits of data out
   assign do_p = doq_wire[(dw+(dw/8))-1:dw];
 
   always @(posedge clk)
     if (rst)
       ce_r <= 0;
     else
       ce_r <= ce;
 
   // Indicate error
   assign p_err = (|parity_err) & ce_r;
 
   // Inject a parity error. Can specify GPR number to affect,
   // and which parity or data bit to switch.
   task gen_parity_err;
      input [aw-1:0] 		word_no;
      input [31:0] 		data_bit_no;
      reg [bw:0] 		do_temp;
      begin
	 // Fish word out
	 if (data_bit_no < 8) begin
	    do_temp = mem0[word_no];
	 end
	 else if (data_bit_no < 16) begin
	    do_temp = mem1[word_no];
	    data_bit_no = data_bit_no - 8;
	 end
	 else if (data_bit_no < 24) begin
	    do_temp = mem2[word_no];
	    data_bit_no = data_bit_no - 16;
	 end
	 else if (data_bit_no < 32) begin
	    do_temp = mem3[word_no];
	    data_bit_no = data_bit_no - 24;
	 end
	 else begin
	    do_temp = mem3[word_no];
	    data_bit_no = 8;
	 end
 
	 // Switch bit
	 do_temp[data_bit_no] = ~do_temp[data_bit_no] ;
 
	 // Replace word
	 if (data_bit_no < 8)
	    mem0[word_no] = do_temp;
	 else if (data_bit_no < 16)
	    mem1[word_no] = do_temp;
	 else if (data_bit_no < 24)
	   mem2[word_no] = do_temp;
	 else
	    mem3[word_no] = do_temp;
      end
   endtask // gen_parity_err
`endif   
 
   //
   // Data output drivers
   //
`ifdef OR1200_RAM_PARITY
   assign doq0_wire = mem0[addr_reg];
   assign doq1_wire = mem1[addr_reg];
   assign doq2_wire = mem2[addr_reg];
   assign doq3_wire = mem3[addr_reg];
 
   assign doq_wire = {// Parity bits
		      doq0_wire[bw],doq1_wire[bw],doq2_wire[bw],doq3_wire[bw],
		      // Data bytes
		      doq0_wire[bw-1:0],doq1_wire[bw-1:0],
		      doq2_wire[bw-1:0],doq3_wire[bw-1:0]};
`else
   assign doq_wire = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
`endif
   assign doq = doq_wire[dw-1:0];
 
 
   //
   // RAM read address register
   //
   always @(posedge clk)
     if (ce)
       addr_reg <=  addr;
 
   //
   // RAM write - big endian selection
   //
   always @(posedge clk)
     if (ce) begin
`ifdef OR1200_RAM_PARITY
	if (we[3])
          mem0[addr] <=  {di_p[3],di[(bw*3)+(bw-1):(bw*3)]};
	if (we[2])
          mem1[addr] <=  {di_p[2],di[(bw*2)+(bw-1):(bw*2)]};
	if (we[1])
          mem2[addr] <=  {di_p[1],di[(bw*1)+(bw-1):(bw*1)]};
	if (we[0])
          mem3[addr] <=  {di_p[0],di[(bw*0)+(bw-1):(bw*0)]};
`else	
	if (we[3])
          mem0[addr] <=  di[(bw*3)+(bw-1):(bw*3)];
	if (we[2])
          mem1[addr] <=  di[(bw*2)+(bw-1):(bw*2)];
	if (we[1])
          mem2[addr] <=  di[(bw*1)+(bw-1):(bw*1)];
	if (we[0])
          mem3[addr] <=  di[(bw*0)+(bw-1):(bw*0)];
`endif	
     end
 
endmodule // or1200_spram_32_bw