URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [README] - Rev 762
Go to most recent revision | Compare with Previous | Blame | View Log
UART 16550 compatible (mostly) core RTLhttp://opencores.org/project,uart16550The core is configured to be in 8-bit mode in this project.
Go to most recent revision | Compare with Previous | Blame | View Log