URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [README] - Rev 367
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UART 16550 compatible (mostly) core RTLhttp://opencores.org/project,uart16550The core is configured to be in 8-bit mode in this project.
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