URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [README] - Rev 361

UART 16550 compatible (mostly) core RTL

http://opencores.org/project,uart16550

The core is configured to be in 8-bit mode in this project.