Subversion Repositories openrisc_2011-10-31

/*
        OR1200 zero and sign extension instruction tests

        Very basic, testing

        Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
        
*/
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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//////////////////////////////////////////////////////////////////////
        
        
#include "spr-defs.h"
#include "board.h"
#include "or1200-defines.h"

        
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"


/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100      
        l.movhi r0, 0
        /* Clear status register */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR

        /* Jump to program initialisation code */
        .global _start
        l.movhi r4, hi(_start)
        l.ori r4, r4, lo(_start)
        l.jr    r4
        l.nop

        .org 0x600      
        l.nop 0x1

        
/* ---[ 0x700: Illegal instruction exception ]-------------------------- */
        .org 0x700
#ifndef OR1200_IMPL_ALU_EXT
        // No problem - instruction not supported
        l.movhi r3, hi(0x8000000d)
        l.ori   r3, r3, lo(0x8000000d)
        l.nop   0x2
        l.ori   r3, r0, 0
#else
        l.ori   r3, r0, 1
#endif
        l.nop   0x1


/* =================================================== [ text ] === */
        .section .text

/* =================================================== [ start ] === */ 

        .global _start
_start: 
        // Kick off test
        l.jal   _main
        l.nop
        


/* =================================================== [ main ] === */
        
        .global _main   
_main:
        // l.exth tests first
        l.ori   r4,r0,0xffff
        l.ori   r5,r0,0x7fff

        l.exths r3,r4

        l.movhi r8,0xffff
        l.ori   r8,r8,0xffff

        l.nop   0x2
        l.sfne  r8,r3
        l.bf    fail
        l.nop

        l.ori   r8,r0,0xffff

        l.exthz r3,r4

        l.nop   0x2
        
        l.sfne  r8,r3
        l.bf    fail
        l.nop

        l.exths r3,r5

        l.nop   0x2

        l.sfne  r3,r5
        l.bf    fail
        l.nop

        l.exthz r3,r5

        l.nop   0x2

        l.sfne  r3,r5
        l.bf    fail
        l.nop

        // l.extb tests
        
        l.ori   r4,r0,0x00ff
        l.ori   r5,r0,0x007f
        
        l.extbs r3,r4

        l.nop   0x2

        l.movhi r8,0xffff
        l.ori   r8,r8,0xffff

        l.sfne  r8,r3
        l.bf    fail
        l.nop

        l.ori   r8,r0,0x00ff

        l.extbz r3,r4

        l.nop   0x2
        
        l.sfne  r8,r3
        l.bf    fail
        l.nop

        l.extbs r3,r5

        l.nop   0x2

        l.sfne  r3,r5
        l.bf    fail
        l.nop

        l.extbz r3,r5

        l.nop   0x2

        l.sfne  r3,r5
        l.bf    fail
        l.nop

        // l.extw tests - shouldn't change anything
        l.movhi r4,0xffff
        l.ori   r4,r4,0xffff

        l.extws r3,r4

        l.nop   0x2
        
        l.sfne  r3,r4
        l.bf    fail
        l.nop

        l.extwz r3,r4

        l.nop   0x2
        
        l.sfne  r3,r4
        l.bf    fail
        l.nop

        
        l.movhi r3, hi(0x8000000d)
        l.ori   r3, r3, lo(0x8000000d)
        l.nop   0x2
        l.ori   r3, r0, 0       
        l.nop   0x1

fail:
        l.ori   r3, r0, 1
        l.nop   0x1