URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [doc/] [html/] [ref/] [nano.html] - Rev 510
Go to most recent revision | Compare with Previous | Blame | View Log
<!-- Copyright (C) 2003 Red Hat, Inc. -->
<!-- This material may be distributed only subject to the terms -->
<!-- and conditions set forth in the Open Publication License, v1.0 -->
<!-- or later (the latest version is presently available at -->
<!-- http://www.opencontent.org/openpub/). -->
<!-- Distribution of the work or derivative of the work in any -->
<!-- standard (paper) book form is prohibited unless prior -->
<!-- permission is obtained from the copyright holder. -->
<HTML
><HEAD
><TITLE
>ARM/StrongARM(SA11X0) Bright Star Engineering commEngine and nanoEngine</TITLE
><meta name="MSSmartTagsPreventParsing" content="TRUE">
<META
NAME="GENERATOR"
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
"><LINK
REL="HOME"
TITLE="eCos Reference Manual"
HREF="ecos-ref.html"><LINK
REL="UP"
TITLE="Installation and Testing"
HREF="installation-and-testing.html"><LINK
REL="PREVIOUS"
TITLE="ARM/StrongARM(SA1110) Intel SA1110 (Assabet) "
HREF="assabet.html"><LINK
REL="NEXT"
TITLE="ARM/StrongARM(SA11X0) Compaq iPAQ PocketPC"
HREF="ipaq.html"></HEAD
><BODY
CLASS="SECT1"
BGCOLOR="#FFFFFF"
TEXT="#000000"
LINK="#0000FF"
VLINK="#840084"
ALINK="#0000FF"
><DIV
CLASS="NAVHEADER"
><TABLE
SUMMARY="Header navigation table"
WIDTH="100%"
BORDER="0"
CELLPADDING="0"
CELLSPACING="0"
><TR
><TH
COLSPAN="3"
ALIGN="center"
>eCos Reference Manual</TH
></TR
><TR
><TD
WIDTH="10%"
ALIGN="left"
VALIGN="bottom"
><A
HREF="assabet.html"
ACCESSKEY="P"
>Prev</A
></TD
><TD
WIDTH="80%"
ALIGN="center"
VALIGN="bottom"
>Chapter 5. Installation and Testing</TD
><TD
WIDTH="10%"
ALIGN="right"
VALIGN="bottom"
><A
HREF="ipaq.html"
ACCESSKEY="N"
>Next</A
></TD
></TR
></TABLE
><HR
ALIGN="LEFT"
WIDTH="100%"></DIV
><DIV
CLASS="SECT1"
><H1
CLASS="SECT1"
><A
NAME="NANO">ARM/StrongARM(SA11X0) Bright Star Engineering commEngine and nanoEngine</H1
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5802">Overview</H2
><P
>RedBoot supports a serial port and the built in ethernet port
for communication and downloads. The default serial port settings are 38400,8,N,1.
RedBoot runs from and supports flash management for the system flash
region.</P
><P
>The following RedBoot configurations are supported:
<DIV
CLASS="INFORMALTABLE"
><A
NAME="AEN5818"><P
></P
><TABLE
BORDER="1"
CLASS="CALSTABLE"
><THEAD
><TR
><TH
ALIGN="LEFT"
VALIGN="TOP"
>Configuration</TH
><TH
ALIGN="LEFT"
VALIGN="TOP"
>Mode</TH
><TH
ALIGN="LEFT"
VALIGN="TOP"
>Description</TH
><TH
ALIGN="LEFT"
VALIGN="TOP"
>File</TH
></TR
></THEAD
><TBODY
><TR
><TD
ALIGN="LEFT"
VALIGN="TOP"
>POST</TD
><TD
ALIGN="LEFT"
VALIGN="TOP"
>[ROM]</TD
><TD
ALIGN="LEFT"
VALIGN="TOP"
>RedBoot running from the first free flash block
at 0x40000.</TD
><TD
ALIGN="LEFT"
VALIGN="TOP"
>redboot_ROM.ecm</TD
></TR
><TR
><TD
ALIGN="LEFT"
VALIGN="TOP"
>RAM</TD
><TD
ALIGN="LEFT"
VALIGN="TOP"
>[RAM]</TD
><TD
ALIGN="LEFT"
VALIGN="TOP"
>RedBoot running from RAM with RedBoot in the
flash boot sector.</TD
><TD
ALIGN="LEFT"
VALIGN="TOP"
>redboot_RAM.ecm</TD
></TR
></TBODY
></TABLE
><P
></P
></DIV
></P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5837">Initial Installation</H2
><P
>Unlike other targets, the nanoEngine comes equipped with boot firmware
which you cannot modify. See chapter 5, "nanoEngine Firmware" of the <I
CLASS="CITETITLE"
>nanoEngine Hardware Reference Manual</I
> (we refer to "July 17, 2000
Rev 0.6") from Bright Star Engineering. </P
><P
>Because of this, eCos, and therefore Redboot, only supports a
special configuration of the ROM mode, starting at offset 0x40000 in
the flash.</P
><P
>Briefly, the POST-configuration RedBoot image lives in flash following the
BSE firmware. The BSE firmware is configured, using its standard <B
CLASS="COMMAND"
>bootcmd</B
> command, to run RedBoot at startup.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5844">Download Instructions</H2
><P
>You can perform the initial load of the POST-configuration RedBoot image into
flash using the BSE firmware's <B
CLASS="COMMAND"
>load</B
> command.
This will load a binary file, using TFTP, and program it into flash in one
operation. Because no memory management is used in the BSE firmware, flash
is mapped from address zero upwards, so the address for the RedBoot POST image
is 0x40000. You must use the binary version of RedBoot for this,
<TT
CLASS="FILENAME"
>redboot-post.bin</TT
>.</P
><P
>This assumes you have set up the other BSE firmware config
parameters such that it can communicate over your network to your TFTP
server.
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="SCREEN"
>><TT
CLASS="USERINPUT"
><B
>load redboot-post.bin 40000</B
></TT
>
loading ... erasing blk at 00040000
erasing blk at 00050000
94168 bytes loaded cksum 00008579
done
>
> <TT
CLASS="USERINPUT"
><B
>set bootcmd "go 40000"</B
></TT
>
> <TT
CLASS="USERINPUT"
><B
>get</B
></TT
>
myip = 10.16.19.198
netmask = 255.255.255.0
eth = 0
gateway = 10.16.19.66
serverip = 10.16.19.66
bootcmd = go 40000
></PRE
></TD
></TR
></TABLE
>
<DIV
CLASS="NOTE"
><BLOCKQUOTE
CLASS="NOTE"
><P
><B
>NOTE: </B
>the BSE firmware runs its serial IO at 9600 Baud; RedBoot runs instead
at 38400 Baud. You must select the right baud rate in your terminal program
to be able to set up the BSE firmware.</P
></BLOCKQUOTE
></DIV
>
After a reset, the BSE firmware will print
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="SCREEN"
>Boot: BSE 2000 Sep 12 2000 14:00:30
autoboot: "go 40000" [hit ESC to abort]</PRE
></TD
></TR
></TABLE
>
and then RedBoot starts, switching to 38400 Baud.</P
><P
>Once you have installed a bootable RedBoot in the system in this
manner, we advise re-installing using the generic method described in
<A
HREF="updating-redboot.html"
>Chapter 4</A
> in order that the Flash Image System
contains an appropriate description of the flash entries.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5860">Cohabiting with POST in Flash</H2
><P
>The configuration file named <TT
CLASS="FILENAME"
>redboot_POST.ecm</TT
>
configures RedBoot to build for execution at address 0x50040000 (or, during
bootup, 0x00040000). This is to allow power-on self-test (POST) code or immutable
firmware to live in the lower addresses of the flash and to run before RedBoot
gets control. The assumption is that RedBoot will be entered at its base address
in physical memory, that is 0x00040000.</P
><P
>Alternatively, for testing, you can call it in an already running system
by using <TT
CLASS="USERINPUT"
><B
>go 0x50040040</B
></TT
> at another RedBoot prompt, or
a branch to that address. The address is where the reset vector
points. It is reported by RedBoot's <B
CLASS="COMMAND"
>load</B
> command
and listed
by the <B
CLASS="COMMAND"
>fis list</B
> command, amongst other
places.</P
><P
>Using the POST configuration enables a normal config option which causes
linking and initialization against memory layout files called "...post..."
rather than "...rom..." or "...ram..." in the <TT
CLASS="FILENAME"
>include/pkgconf</TT
> directory. Specifically:<P
CLASS="LITERALLAYOUT"
><TT
CLASS="FILENAME"
>include/pkgconf/mlt_arm_sa11x0_nano_post.h</TT
><br>
<TT
CLASS="FILENAME"
>include/pkgconf/mlt_arm_sa11x0_nano_post.ldi</TT
><br>
<TT
CLASS="FILENAME"
>include/pkgconf/mlt_arm_sa11x0_nano_post.mlt</TT
></P
>
It is these you should edit if you wish to move the execution address
from 0x50040000 in the POST configuration. Startup mode naturally
remains ROM in this configuration.</P
><P
>Because the nanoEngine contains immutable boot firmware at the start
of flash, RedBoot for this target is configured to reserve that area in the
Flash Image System, and to create by default an entry for the POST
mode RedBoot.
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="SCREEN"
>RedBoot> <TT
CLASS="USERINPUT"
><B
>fis list</B
></TT
>
Name FLASH addr Mem addr Length Entry point
(reserved) 0x50000000 0x50000000 0x00040000 0x00000000
RedBoot[post] 0x50040000 0x00100000 0x00020000 0x50040040
RedBoot config 0x503E0000 0x503E0000 0x00010000 0x00000000
FIS directory 0x503F0000 0x503F0000 0x00010000 0x00000000
RedBoot></PRE
></TD
></TR
></TABLE
>
The entry "(reserved)" ensures that the FIS cannot attempt
to overwrite the BSE firmware, thus ensuring that the board remains bootable
and recoverable even after installing a broken RedBoot image.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5877">Special RedBoot Commands</H2
><P
>The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers
installed, but these have no associated serial EEPROM in which to record their
Ethernet Station Address (ESA, or MAC address). The BSE firmware records an
ESA for the device it uses, but this information is not available to RedBoot;
we cannot share it.</P
><P
>To keep the ESAs for the two ethernet interfaces, two new items of RedBoot
configuration data are introduced. You can list them with the RedBoot command <B
CLASS="COMMAND"
>fconfig -l</B
> thus:
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="SCREEN"
>RedBoot> <TT
CLASS="USERINPUT"
><B
>fconfig -l</B
></TT
>
Run script at boot: false
Use BOOTP for network configuration: false
Local IP address: 10.16.19.91
Default server IP address: 10.16.19.66
Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99
Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A
GDB connection port: 9000
Network debug at boot time: false
RedBoot></PRE
></TD
></TR
></TABLE
>
You should set them before running RedBoot or eCos applications with
the board connected to a network. The <B
CLASS="COMMAND"
>fconfig </B
>
command can be used as for any configuration data item; the entire ESA
is entered in one line.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5885">Memory Maps</H2
><P
>The first level page table is located at physical address 0xc0004000.
No second level tables are used. <DIV
CLASS="NOTE"
><BLOCKQUOTE
CLASS="NOTE"
><P
><B
>NOTE: </B
>The virtual memory maps in this section use a C and B column to indicate
whether or not the region is cached (C) or buffered (B).</P
></BLOCKQUOTE
></DIV
><TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>Physical Address Range Description
----------------------- ----------------------------------
0x00000000 - 0x003fffff 4Mb FLASH (nCS0)
0x18000000 - 0x18ffffff Internal PCI bus - 2 x i82559 ethernet
0x40000000 - 0x4fffffff External IO or PCI bus
0x80000000 - 0xbfffffff SA-1110 Internal Registers
0xc0000000 - 0xc7ffffff DRAM Bank 0 - 32Mb SDRAM
0xc8000000 - 0xcfffffff DRAM Bank 1 - empty
0xe0000000 - 0xe7ffffff Cache Clean
Virtual Address Range C B Description
----------------------- - - ----------------------------------
0x00000000 - 0x001fffff Y Y DRAM - 8Mb to 32Mb
0x18000000 - 0x180fffff N N Internal PCI bus - 2 x i82559 ethernet
0x40000000 - 0x4fffffff N N External IO or PCI bus
0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0)
0x80000000 - 0xbfffffff N N SA-1110 Internal Registers
0xc0000000 - 0xc0ffffff N Y DRAM Bank 0: 8 or 16Mb
0xc8000000 - 0xc8ffffff N Y DRAM Bank 1: 8 or 16Mb or absent
0xe0000000 - 0xe7ffffff Y Y Cache Clean</PRE
></TD
></TR
></TABLE
></P
><P
>The ethernet devices use a "PCI window" to communicate with the CPU.
This is 1Mb of SDRAM which is shared with the ethernet devices that are on
the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI
accesses see correct data in the correct order. By default it is configured
to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be
modified, and indeed must be, if less than 32Mb of SDRAM is installed, via
the memory layout tool, or by moving the section <TT
CLASS="COMPUTEROUTPUT"
>__pci_window</TT
> referred to by symbols <TT
CLASS="COMPUTEROUTPUT"
>CYGMEM_SECTION_pci_window*</TT
> in the linker script. </P
><P
>Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM
bank 0, the code can cope with any of these combinations also; "2 x " in this
context means one device in each DRAM Bank. <P
CLASS="LITERALLAYOUT"
>1 x 8Mb = 8Mb 2 x 8Mb = 16Mb<br>
1 x 16Mb = 16Mb 2 x 16Mb = 32Mb</P
>All are programmed the same
in the memory controller. </P
><P
>Startup code detects which is fitted and programs the memory map accordingly.
If the device(s) is 8Mb, then there are gaps in the physical memory map, because
a high order address bit is not connected. The gaps are the higher 2Mb out
of every 4Mb.</P
><P
> The SA11x0 OS timer is used as a polled timer to provide timeout
support within RedBoot.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5899">Nano Platform Port</H2
><P
>The nano is in the set of SA11X0-based platforms. It uses the arm architectural
HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components
<P
CLASS="LITERALLAYOUT"
>CYGPKG_HAL_ARM hal/arm/arch/<br>
CYGPKG_HAL_ARM_SA11X0 hal/arm/sa11x0/var<br>
CYGPKG_HAL_ARM_SA11X0_NANO hal/arm/sa11x0/nano</P
> respectively.
</P
><P
>The target name is "nano" which includes all these, plus the ethernet
driver packages, flash driver, and so on.</P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5904">Ethernet Driver</H2
><P
>The ethernet driver is in two parts: </P
><P
>A generic ether driver for Intel i8255x series devices, specifically
the i82559, is <TT
CLASS="COMPUTEROUTPUT"
>devs/eth/intel/i82559</TT
>. Its
package name is <TT
CLASS="COMPUTEROUTPUT"
>CYGPKG_DEVS_ETH_INTEL_I82559</TT
>.
</P
><P
>The platform-specific ether driver is <TT
CLASS="COMPUTEROUTPUT"
>devs/eth/arm/nano</TT
>. Its package is <TT
CLASS="COMPUTEROUTPUT"
>CYGPKG_DEVS_ETH_ARM_NANO</TT
>. This tells the generic driver the address in IO memory
of the chip, for example, and other configuration details. This driver picks
up the ESA from RedBoot's configuration data - unless configured to use a
static ESA in the usual manner. </P
></DIV
><DIV
CLASS="SECT2"
><H2
CLASS="SECT2"
><A
NAME="AEN5913">Rebuilding RedBoot</H2
><P
>These shell variables provide the platform-specific information
needed for building RedBoot according to the procedure described in
<A
HREF="rebuilding-redboot.html"
>Chapter 3</A
>:
<TABLE
BORDER="5"
BGCOLOR="#E0E0F0"
WIDTH="70%"
><TR
><TD
><PRE
CLASS="PROGRAMLISTING"
>export TARGET=nano
export ARCH_DIR=arm
export PLATFORM_DIR=sa11x0/nano</PRE
></TD
></TR
></TABLE
></P
><P
>The names of configuration files are listed above with the
description of the associated modes.</P
></DIV
></DIV
><DIV
CLASS="NAVFOOTER"
><HR
ALIGN="LEFT"
WIDTH="100%"><TABLE
SUMMARY="Footer navigation table"
WIDTH="100%"
BORDER="0"
CELLPADDING="0"
CELLSPACING="0"
><TR
><TD
WIDTH="33%"
ALIGN="left"
VALIGN="top"
><A
HREF="assabet.html"
ACCESSKEY="P"
>Prev</A
></TD
><TD
WIDTH="34%"
ALIGN="center"
VALIGN="top"
><A
HREF="ecos-ref.html"
ACCESSKEY="H"
>Home</A
></TD
><TD
WIDTH="33%"
ALIGN="right"
VALIGN="top"
><A
HREF="ipaq.html"
ACCESSKEY="N"
>Next</A
></TD
></TR
><TR
><TD
WIDTH="33%"
ALIGN="left"
VALIGN="top"
>ARM/StrongARM(SA1110) Intel SA1110 (Assabet)</TD
><TD
WIDTH="34%"
ALIGN="center"
VALIGN="top"
><A
HREF="installation-and-testing.html"
ACCESSKEY="U"
>Up</A
></TD
><TD
WIDTH="33%"
ALIGN="right"
VALIGN="top"
>ARM/StrongARM(SA11X0) Compaq iPAQ PocketPC</TD
></TR
></TABLE
></DIV
></BODY
></HTML
> Go to most recent revision | Compare with Previous | Blame | View Log