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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [aeb/] [v2_0/] [src/] [hal_diag.c] - Rev 454
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/*============================================================================= // // hal_diag.c // // HAL diagnostic output code // //============================================================================= //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with eCos; if not, write to the Free Software Foundation, Inc., // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //============================================================================= //#####DESCRIPTIONBEGIN#### // // Author(s): nickg, gthomas // Contributors:nickg, gthomas // Date: 1998-03-02 // Purpose: HAL diagnostic output // Description: Implementations of HAL diagnostic output support. // //####DESCRIPTIONEND#### // //===========================================================================*/ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.h> // base types #include <cyg/infra/cyg_trac.h> // tracing macros #include <cyg/infra/cyg_ass.h> // assertion macros #include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros #include <cyg/hal/hal_io.h> // IO macros #include <cyg/hal/hal_if.h> // interface API #include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS #include <cyg/hal/hal_misc.h> // Helper functions #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED /*---------------------------------------------------------------------------*/ // AEB Serial Port (UART1) for Debug /*---------------------------------------------------------------------------*/ /* From serial_16550.h */ // UART1, 38400 (Using raw 24MHz system clock) #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB (0) #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB (13*3) // This is the base address of UART1 #define CYG_DEV_UART1_BASE 0xFFFF0400 // Interrupt Enable Register #define SIO_IER_RCV 0x01 #define SIO_IER_XMT 0x02 #define SIO_IER_LS 0x04 #define SIO_IER_MS 0x08 // Define the serial registers. #define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0 #define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0 #define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 #define CYG_DEV_IER 0x04 // interrupt enable register, read/write, dlab = 0 #define CYG_DEV_DLM 0x04 // divisor latch (MS), read/write, dlab = 1 #define CYG_DEV_IIR 0x08 // interrupt identification register, read, dlab = 0 #define CYG_DEV_FCR 0x08 // fifo control register, write, dlab = 0 #define CYG_DEV_LCR 0x0C // line control register, read/write #define CYG_DEV_MCR 0x10 // modem control register, read/write #define CYG_DEV_LSR 0x14 // line status register, read #define CYG_DEV_MSR 0x18 // modem status register, read // The line status register bits. #define SIO_LSR_DR 0x01 // data ready #define SIO_LSR_OE 0x02 // overrun error #define SIO_LSR_PE 0x04 // parity error #define SIO_LSR_FE 0x08 // framing error #define SIO_LSR_BI 0x10 // break interrupt #define SIO_LSR_THRE 0x20 // transmitter holding register empty #define SIO_LSR_TEMT 0x40 // transmitter register empty #define SIO_LSR_ERR 0x80 // any error condition // The modem status register bits. #define SIO_MSR_DCTS 0x01 // delta clear to send #define SIO_MSR_DDSR 0x02 // delta data set ready #define SIO_MSR_TERI 0x04 // trailing edge ring indicator #define SIO_MSR_DDCD 0x08 // delta data carrier detect #define SIO_MSR_CTS 0x10 // clear to send #define SIO_MSR_DSR 0x20 // data set ready #define SIO_MSR_RI 0x40 // ring indicator #define SIO_MSR_DCD 0x80 // data carrier detect // The line control register bits. #define SIO_LCR_WLS0 0x01 // word length select bit 0 #define SIO_LCR_WLS1 0x02 // word length select bit 1 #define SIO_LCR_STB 0x04 // number of stop bits #define SIO_LCR_PEN 0x08 // parity enable #define SIO_LCR_EPS 0x10 // even parity select #define SIO_LCR_SP 0x20 // stick parity #define SIO_LCR_SB 0x40 // set break #define SIO_LCR_DLAB 0x80 // divisor latch access bit // Modem Control Register #define SIO_MCR_DTR 0x01 #define SIO_MCR_RTS 0x02 #define SIO_MCR_INT 0x08 // Enable interrupts //----------------------------------------------------------------------------- typedef struct { cyg_uint8* base; cyg_int32 msec_timeout; int isr_vector; } channel_data_t; //----------------------------------------------------------------------------- static void cyg_hal_plf_serial_init_channel(void* __ch_data) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint8 lcr, dll, dlm; // 8-1-no parity. HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1); HAL_READ_UINT8(base+CYG_DEV_LCR, lcr); lcr |= SIO_LCR_DLAB; HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr); HAL_READ_UINT8(base+CYG_DEV_DLL, dll); HAL_READ_UINT8(base+CYG_DEV_DLM, dlm); HAL_WRITE_UINT8 (base+CYG_DEV_DLL, CYG_DEVICE_SERIAL_RS232_BAUD_LSB); HAL_WRITE_UINT8 (base+CYG_DEV_DLM, CYG_DEVICE_SERIAL_RS232_BAUD_MSB); lcr &= ~SIO_LCR_DLAB; HAL_WRITE_UINT8 (base+CYG_DEV_LCR, lcr); HAL_WRITE_UINT8 (base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO } void cyg_hal_plf_serial_putc(void *__ch_data, char c) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint8 lsr; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT8(base+CYG_DEV_LSR, lsr); } while ((lsr & SIO_LSR_THRE) == 0); HAL_WRITE_UINT8(base+CYG_DEV_THR, c); CYGARC_HAL_RESTORE_GP(); } static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint8 lsr; HAL_READ_UINT8(base+CYG_DEV_LSR, lsr); if ((lsr & SIO_LSR_DR) == 0) return false; HAL_READ_UINT8(base+CYG_DEV_RBR, *ch); return true; } cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data) { cyg_uint8 ch; CYGARC_HAL_SAVE_GP(); while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); CYGARC_HAL_RESTORE_GP(); return ch; } static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, cyg_uint32 __len) { CYGARC_HAL_SAVE_GP(); while(__len-- > 0) cyg_hal_plf_serial_putc(__ch_data, *__buf++); CYGARC_HAL_RESTORE_GP(); } static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) { CYGARC_HAL_SAVE_GP(); while(__len-- > 0) *__buf++ = cyg_hal_plf_serial_getc(__ch_data); CYGARC_HAL_RESTORE_GP(); } cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) { int delay_count; channel_data_t* chan = (channel_data_t*)__ch_data; cyg_bool res; CYGARC_HAL_SAVE_GP(); delay_count = chan->msec_timeout * 10; // delay in .1 ms steps for(;;) { res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); if (res || 0 == delay_count--) break; CYGACC_CALL_IF_DELAY_US(100); } CYGARC_HAL_RESTORE_GP(); return res; } static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; channel_data_t* chan = (channel_data_t*)__ch_data; int ret = 0; CYGARC_HAL_SAVE_GP(); switch (__func) { case __COMMCTL_IRQ_ENABLE: irq_state = 1; HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV); HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS); HAL_INTERRUPT_UNMASK(chan->isr_vector); break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0); HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS); HAL_INTERRUPT_MASK(chan->isr_vector); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: { va_list ap; va_start(ap, __func); ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); va_end(ap); } default: break; } CYGARC_HAL_RESTORE_GP(); return ret; } static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { int res = 0; channel_data_t* chan = (channel_data_t*)__ch_data; char c; cyg_uint8 lsr; CYGARC_HAL_SAVE_GP(); cyg_drv_interrupt_acknowledge(chan->isr_vector); *__ctrlc = 0; HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr); if ( (lsr & SIO_LSR_DR) != 0 ) { HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c); if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1; res = CYG_ISR_HANDLED; } CYGARC_HAL_RESTORE_GP(); return res; } static channel_data_t aeb_ser_channels[1]; static void cyg_hal_plf_serial_init(void) { hal_virtual_comm_table_t* comm; int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); channel_data_t* chan; chan = &aeb_ser_channels[0]; chan->base = (cyg_uint8*)CYG_DEV_UART1_BASE; chan->isr_vector = CYGNUM_HAL_INTERRUPT_UART1; chan->msec_timeout = 1000; // Init channel cyg_hal_plf_serial_init_channel(chan); // Setup procs in the vector table // Set channel 0 CYGACC_CALL_IF_SET_CONSOLE_COMM(0); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, chan); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); // Restore original console CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); } void cyg_hal_plf_comms_init(void) { static int initialized = 0; if (initialized) return; initialized = 1; cyg_hal_plf_serial_init(); } //============================================================================= // Compatibility with older stubs //============================================================================= #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS #include <cyg/hal/drv_api.h> #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt #endif // Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e. // totally stand-alone) system. #if defined(CYG_HAL_STARTUP_ROM) || !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN) #define HAL_DIAG_USES_HARDWARE #endif static channel_data_t aeb_ser_channel = {(cyg_uint8*)CYG_DEV_UART1_BASE, 0, 0}; #ifdef HAL_DIAG_USES_HARDWARE void hal_diag_init(void) { static int init = 0; char *msg = "\n\rAEB-1 eCos\n\r"; if (init++) return; cyg_hal_plf_serial_init_channel(&aeb_ser_channel); while (*msg) cyg_hal_plf_serial_putc(&aeb_ser_channel, *msg++); } #ifdef DEBUG_DIAG #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) #define DIAG_BUFSIZE 32 #else #define DIAG_BUFSIZE 2048 #endif static char diag_buffer[DIAG_BUFSIZE]; static int diag_bp = 0; #endif void hal_diag_write_char(char c) { hal_diag_init(); cyg_hal_plf_serial_putc(&aeb_ser_channel, c); #ifdef DEBUG_DIAG diag_buffer[diag_bp++] = c; if (diag_bp == DIAG_BUFSIZE) diag_bp = 0; #endif } void hal_diag_read_char(char *c) { *c = cyg_hal_plf_serial_getc(&aeb_ser_channel); } #else // HAL_DIAG relies on GDB // Initialize diag port - assume GDB channel is already set up void hal_diag_init(void) { if (0) cyg_hal_plf_serial_init_channel(&aeb_ser_channel); // avoid warning } // Actually send character down the wire static void hal_diag_write_char_serial(char c) { hal_diag_init(); cyg_hal_plf_serial_putc(&aeb_ser_channel, c); } static bool hal_diag_read_serial(char *c) { long timeout = 1000000000; // A long time... while (!cyg_hal_plf_serial_getc_nonblock(&aeb_ser_channel, c)) if (0 == --timeout) return false; return true; } void hal_diag_read_char(char *c) { while (!hal_diag_read_serial(c)) ; } void hal_diag_write_char(char c) { static char line[100]; static int pos = 0; // No need to send CRs if( c == '\r' ) return; line[pos++] = c; if( c == '\n' || pos == sizeof(line) ) { CYG_INTERRUPT_STATE old; // Disable interrupts. This prevents GDB trying to interrupt us // while we are in the middle of sending a packet. The serial // receive interrupt will be seen when we re-enable interrupts // later. #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); #else HAL_DISABLE_INTERRUPTS(old); #endif while(1) { static char hex[] = "0123456789ABCDEF"; cyg_uint8 csum = 0; int i; char c1; hal_diag_write_char_serial('$'); hal_diag_write_char_serial('O'); csum += 'O'; for( i = 0; i < pos; i++ ) { char ch = line[i]; char h = hex[(ch>>4)&0xF]; char l = hex[ch&0xF]; hal_diag_write_char_serial(h); hal_diag_write_char_serial(l); csum += h; csum += l; } hal_diag_write_char_serial('#'); hal_diag_write_char_serial(hex[(csum>>4)&0xF]); hal_diag_write_char_serial(hex[csum&0xF]); // Wait for the ACK character '+' from GDB here and handle // receiving a ^C instead. This is the reason for this clause // being a loop. if (!hal_diag_read_serial(&c1)) continue; // No response - try sending packet again if( c1 == '+' ) break; // a good acknowledge #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_UART1); if( c1 == 3 ) { // Ctrl-C: breakpoint. cyg_hal_gdb_interrupt (__builtin_return_address(0)); break; } #endif // otherwise, loop round again } pos = 0; // And re-enable interrupts #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); #else HAL_RESTORE_INTERRUPTS(old); #endif } } #endif #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG /*---------------------------------------------------------------------------*/ /* End of hal_diag.c */
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