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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [edb7xxx/] [v2_0/] [include/] [pkgconf/] [mlt_arm_edb7212_rom.ldi] - Rev 174
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// eCos memory layout - Fri Oct 20 05:42:50 2000
// This is a generated file - do not edit
#include <cyg/infra/cyg_type.inc>
MEMORY
{
ram : ORIGIN = 0, LENGTH = 0xfd7000
sram : ORIGIN = 0x60000000, LENGTH = 0x9c00
rom : ORIGIN = 0xe0000000, LENGTH = 0x800000
}
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0xe0000000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_mmu_tables (rom, ALIGN (0x4000), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
SECTION_data (ram, 0x1000, FOLLOWING (.mmu_tables))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTION_sram (sram, 0x60000000, LMA_EQ_VMA)
SECTIONS_END
}