URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [sa11x0/] [flexanet/] [v2_0/] [include/] [pkgconf/] [mlt_arm_sa11x0_flexanet_ram.h] - Rev 587
Go to most recent revision | Compare with Previous | Blame | View Log
// eCos memory layout - Fri Oct 20 05:56:24 2000 // This is a generated file - do not edit #ifndef __ASSEMBLER__ #include <cyg/infra/cyg_type.h> #include <stddef.h> #endif #define CYGMEM_REGION_ram (0) #define CYGMEM_REGION_ram_SIZE (0x2000000) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) #ifndef __ASSEMBLER__ extern char CYG_LABEL_NAME (__heap1) []; #endif #define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) #define CYGMEM_SECTION_heap1_SIZE (0x2000000 - (size_t) CYG_LABEL_NAME (__heap1))
Go to most recent revision | Compare with Previous | Blame | View Log