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#ifndef CYGONCE_HAL_PROC_ARCH_H
#define CYGONCE_HAL_PROC_ARCH_H
//=============================================================================
//
//      proc_arch.h
//
//      Processor variant specific abstractions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
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// or inline functions from this file, or you compile this file and link it
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//
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// this file might be covered by the GNU General Public License.
//
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// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/mcf5272_sim.h>
//#include <cyg/hal/hal_memmap.h>
 
// Declare the global pointer to the SIM registers.
// Everyone should use the MCF5272_SIM macro so it can be easily changed.
externC volatile mcf5272_sim_t * const mcf5272_sim_p;
#define MCF5272_SIM mcf5272_sim_p
//#define MCF5272_SIM ((volatile mcf5272_sim_t *) MCF5272_MBAR)
 
/* ************************************************************************ */
/* These routines write to  the special purpose  registers in the  ColdFire */
/* core.  Since these registers are write-only in the supervisor model,  no */
/* corresponding read routines exist.                                       */
 
externC void mcf5272_wr_mbar(CYG_WORD32);
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PROC_ARCH_H