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//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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//
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// or inline functions from this file, or you compile this file and link it
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//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
#include <pkgconf/hal.h>
#include <cyg/hal/hal_startup.h>
#include <cyg/hal/hal_memmap.h>
#include <cyg/hal/hal_arch.h>
 
/*****************************************************************************
var_init_cache_acr --  Initialize the cache and access control registers
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
     None
 
*****************************************************************************/
static void var_init_cache_acr(void)
{
 
    //   Invalidate and disable the cache and ACRs.
 
    mcf52xx_wr_cacr((CYG_WORD32)0x01000000);
    mcf52xx_wr_acr0((CYG_WORD32)0);
    mcf52xx_wr_acr1((CYG_WORD32)0);
 
    //   Call a routine to set  up  the  cache  and  ACRs  for  this  specific
    // platform.
 
    plf_init_cache_acr();
 
}
 
/*****************************************************************************
var_reset --  Variant-specific reset vector initialization routine
 
     This routine must be called with interrupts disabled.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
     None
 
*****************************************************************************/
void var_reset(void)
{
 
    //   Initialize the processor's vector base register.
 
    mcf52xx_wr_vbr((CYG_WORD32)__ramvec_start);
 
    //   Initialize the cache and access control registers.
 
    var_init_cache_acr();
 
    //   Do any processor-specific reset initialization.
 
    proc_reset();
}