OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mn10300/] [sim/] [v2_0/] [include/] [pkgconf/] [mlt_mn10300_am31_sim_ram.ldi] - Rev 174

Compare with Previous | Blame | View Log

// eCos memory layout - Fri Oct 20 08:25:16 2000

// This is a generated file - do not edit

#include <cyg/infra/cyg_type.inc>

MEMORY
{
    ram : ORIGIN = 0x48000000, LENGTH = 0x400000
}

SECTIONS
{
    SECTIONS_BEGIN
    SECTION_rom_vectors (ram, 0x48000000, LMA_EQ_VMA)
    SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    SECTIONS_END
}

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.