URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [sim/] [v2_0/] [include/] [pkgconf/] [mlt_powerpc_sim_ram.ldi] - Rev 249
Go to most recent revision | Compare with Previous | Blame | View Log
// eCos memory layout - Fri Oct 20 10:36:41 2000// This is a generated file - do not edit#include <cyg/infra/cyg_type.inc>MEMORY{ram : ORIGIN = 0, LENGTH = 0x100000}SECTIONS{SECTIONS_BEGINSECTION_vectors (ram, 0, LMA_EQ_VMA)CYG_LABEL_DEFN(__reserved_vsr_table) = 0x3000; . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);SECTIONS_END}
Go to most recent revision | Compare with Previous | Blame | View Log