OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [powerpc/] [sim/] [v2_0/] [include/] [pkgconf/] [mlt_powerpc_sim_ram.mlt] - Rev 174

Compare with Previous | Blame | View Log

version 0
region ram 0 100000 0 !
section vectors 0 1 0 1 1 0 1 0 0 0 !
section reserved_vsr_table 200 1 0 0 1 1 1 1 3000 3000 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 1 0 1 data data !
section data 0 8 0 1 0 1 0 1 sbss sbss !
section sbss 0 4 0 1 0 1 0 1 bss bss !
section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.