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#ifndef CYGONCE_HAL_ARM_XSCALE_XSENGINE_XSENGINE_H
#define CYGONCE_HAL_ARM_XSCALE_XSENGINE_XSENGINE_H
 
//=============================================================================
//
//      xsengine.h
//
//      Platform specific support (register layout, etc)
//
//=============================================================================
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// -------------------------------------------                              
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//=============================================================================
 
#include <pkgconf/system.h>
#include CYGHWR_MEMORY_LAYOUT_H
#include <pkgconf/hal_arm_xscale_xsengine.h>
#include <cyg/hal/hal_pxa2x0.h>           // Applications Processor defines
 
#define SDRAM_PHYS_BASE     0xa0000000
#define SDRAM_BASE          0x00000000
#define SDRAM_SIZE          0x04000000    // 64 MB
#define SDRAM_MAX           0x10000000 
 
#define XSENGINE_FLASH_ADDR 0x50000000
 
// These must match setup in the page table in hal_platform_extras.h
#define SDRAM_UNCACHED_BASE 0xc0000000
#undef  DCACHE_FLUSH_AREA
#define DCACHE_FLUSH_AREA   0xe0000000
// ------------------------------------------------------------------------
 
#endif // CYGONCE_HAL_ARM_XSCALE_XSENGINE_XSENGINE_H