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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [cortexm/] [a2fxxx/] [var/] [current/] [include/] [var_intr.h] - Rev 786
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#ifndef CYGONCE_HAL_VAR_INTR_H #define CYGONCE_HAL_VAR_INTR_H //========================================================================== // // var_intr.h // // HAL Interrupt and clock assignments for Smartfusion Cortex-M3 variants // //========================================================================== // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 2011 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later // version. // // eCos is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License // along with eCos; if not, write to the Free Software Foundation, Inc., // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. // // As a special exception, if other files instantiate templates or use // macros or inline functions from this file, or you compile this file // and link it with other works to produce a work based on this file, // this file does not by itself cause the resulting work to be covered by // the GNU General Public License. However the source code for this file // must still be made available in accordance with section (3) of the GNU // General Public License v2. // // This exception does not invalidate any other reasons why a work based // on this file might be covered by the GNU General Public License. // ------------------------------------------- // ####ECOSGPLCOPYRIGHTEND#### //========================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): ccoutand // Date: 2011-01-18 // Purpose: Define Interrupt support // Description: The interrupt specifics for Actel Smartfusion Cortex-M3 // are defined here. // // Usage: #include <cyg/hal/var_intr.h> // However applications should include using <cyg/hal/hal_intr.h> // instead to allow for platform overrides. // //####DESCRIPTIONEND#### // //========================================================================== #include <cyg/hal/plf_intr.h> //========================================================================== #define CYGNUM_HAL_INTERRUPT_WD (0+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_VR_PSM_5V (1+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_VR_PSM_3V (2+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RTC0_0 (3+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RTC0_1 (4+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_MAC0 (5+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_IAP (6+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ENVM0 (7+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ENVM1 (8+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_DMA (9+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_UART0 (10+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_UART1 (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_SPI0 (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_SPI1 (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_I2C0_0 (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_I2C0_1 (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_I2C0_2 (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_I2C1_0 (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_I2C1_1 (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_I2C1_2 (19+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_TIM0_1 (20+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_TIM0_2 (21+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_MSS_CCC_0 (22+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_MSS_CCC_1 (23+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_AHB (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RESERVED0 (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RESERVED1 (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RESERVED2 (27+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RESERVED3 (28+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RESERVED4 (29+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_RESERVED5 (30+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_FAB (31+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO0 (32+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO1 (33+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO2 (34+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO3 (35+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO4 (36+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO5 (37+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO6 (38+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO7 (39+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO8 (40+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO9 (41+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO10 (42+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO11 (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO12 (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO13 (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO14 (46+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO15 (47+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO16 (48+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO17 (49+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO18 (50+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO19 (51+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO20 (52+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO21 (53+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO22 (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO23 (55+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO24 (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO25 (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO26 (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO27 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO28 (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO29 (61+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO30 (62+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_GPIO31 (63+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG0 (64+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG1 (65+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG2 (66+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC0_FLAG3 (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG0 (68+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG1 (69+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG2 (70+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC1_FLAG3 (71+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG0 (72+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG1 (73+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG2 (74+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PC2_FLAG3 (75+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC0_DV (76+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC1_DV (77+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC2_DV (78+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CD (79+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CD (80+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CD (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC0_CS (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC1_CS (83+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC2_CS (84+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP0_FALL (85+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP1_FALL (86+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP2_FALL (87+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP3_FALL (88+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP4_FALL (89+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP5_FALL (90+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP6_FALL (91+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP7_FALL (92+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP8_FALL (93+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP9_FALL (94+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP10_FALL (95+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP11_FALL (96+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP0_RISE (97+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP1_RISE (98+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP2_RISE (99+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP3_RISE (100+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP4_RISE (101+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP5_RISE (102+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP6_RISE (103+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP7_RISE (104+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP8_RISE (105+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP9_RISE (106+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP10_RISE (107+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_COMP11_RISE (108+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FF (109+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FAF (110+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC0_FE (111+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FF (112+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FAF (113+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC1_FE (114+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FF (115+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FAF (116+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_ADC2_FE (117+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG0 (118+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG1 (119+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG2 (120+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG3 (121+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG4 (122+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG5 (123+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG6 (124+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG7 (125+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG8 (126+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG9 (127+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG10 (128+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG11 (129+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG12 (130+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG13 (131+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG14 (132+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG15 (133+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG16 (134+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG17 (135+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG18 (136+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG19 (137+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG20 (138+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG21 (139+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG22 (140+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG23 (141+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG24 (142+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG25 (143+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG26 (144+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG27 (145+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG28 (146+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG29 (147+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG30 (148+CYGNUM_HAL_INTERRUPT_EXTERNAL) #define CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31 (149+CYGNUM_HAL_INTERRUPT_EXTERNAL) #ifndef CYGNUM_HAL_INTERRUPT_NVIC_MAX #define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_ACE_PPE_FLAG31) #endif #define CYGNUM_HAL_ISR_MIN 0 #ifndef CYGNUM_HAL_ISR_MAX #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_NVIC_MAX #endif #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) #define CYGNUM_HAL_VSR_MIN 0 #ifndef CYGNUM_HAL_VSR_MAX #define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX) #endif #define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) //---------------------------------------------------------------------------- #endif // CYGONCE_HAL_VAR_INTR_H // EOF var_intr.h