URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [h8300/] [sim_s/] [current/] [include/] [pkgconf/] [mlt_h8300_h8s_sim_ram.ldi] - Rev 786
Compare with Previous | Blame | View Log
// eCos memory layout - Fri Oct 20 08:25:16 2000// This is a generated file - do not edit#include <cyg/infra/cyg_type.inc>OUTPUT_FORMAT("elf32-h8300")OUTPUT_ARCH(h8300s)MEMORY{ram : ORIGIN = 0x000000, LENGTH = 0x200000}SECTIONS{SECTIONS_BEGINSECTION_rom_vectors (ram, 0x000000, LMA_EQ_VMA)SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_int_hook_table (ram, ALIGN (0x1), LMA_EQ_VMA)SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);SECTIONS_END}