OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [mips/] [vrc4375/] [current/] [include/] [pkgconf/] [mlt_mips_vr4300_vrc4375_romram.ldi] - Rev 786

Compare with Previous | Blame | View Log

// eCos memory layout - Fri Oct 20 06:27:12 2000

// This is a generated file - do not edit

#include <cyg/infra/cyg_type.inc>

MEMORY
{
    ram : ORIGIN = 0x80000000, LENGTH = 0x1f00000
}

SECTIONS
{
    SECTIONS_BEGIN
    SECTION_rom_vectors (ram, 0x80000000, LMA_EQ_VMA)
    SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_ctors (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_dtors (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_rel__dyn (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
    SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
    SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
    CYG_LABEL_DEFN(__pci_window) = 0x81f00000; . = CYG_LABEL_DEFN(__pci_window) + 0x100000;
    SECTIONS_END
}

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.