URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [openrisc/] [arch/] [current/] [cdl/] [hal_openrisc.cdl] - Rev 790
Go to most recent revision | Compare with Previous | Blame | View Log
# ====================================================================## hal_openrisc.cdl## OpenRISC architectural HAL package configuration data## ====================================================================## ####ECOSGPLCOPYRIGHTBEGIN###### -------------------------------------------## This file is part of eCos, the Embedded Configurable Operating System.## Copyright (C) 2003 Free Software Foundation, Inc.#### eCos is free software; you can redistribute it and/or modify it under## the terms of the GNU General Public License as published by the Free## Software Foundation; either version 2 or (at your option) any later## version.#### eCos is distributed in the hope that it will be useful, but WITHOUT## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License## for more details.#### You should have received a copy of the GNU General Public License## along with eCos; if not, write to the Free Software Foundation, Inc.,## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.#### As a special exception, if other files instantiate templates or use## macros or inline functions from this file, or you compile this file## and link it with other works to produce a work based on this file,## this file does not by itself cause the resulting work to be covered by## the GNU General Public License. However the source code for this file## must still be made available in accordance with section (3) of the GNU## General Public License v2.#### This exception does not invalidate any other reasons why a work based## on this file might be covered by the GNU General Public License.## -------------------------------------------## ####ECOSGPLCOPYRIGHTEND##### ====================================================================######DESCRIPTIONBEGIN###### Author(s): sfurman# Original data: bartv, nickg# Contributors: jskov# Date: 2003-02-28######DESCRIPTIONEND###### ====================================================================cdl_package CYGPKG_HAL_OPENRISC {display "OpenRISC architecture"parent CYGPKG_HALhardwareinclude_dir cyg/haldefine_header hal_openrisc.hdescription "The OpenRISC architecture HAL package provides generic supportfor this processor architecture. It is also necessary toselect a specific target platform HAL package."compile context.S vectors.S hal_misc.c openrisc_stub.cimplements CYGINT_HAL_DEBUG_GDB_STUBSimplements CYGINT_HAL_DEBUG_GDB_STUBS_BREAKmake {<PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S$(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<@echo $@ ": \\" > $(notdir $@).deps@tail -n +2 vectors.tmp >> $(notdir $@).deps@echo >> $(notdir $@).deps@rm vectors.tmp}define_proc {puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK hal_arch_program_new_stack"}cdl_option CYGBLD_LINKER_SCRIPT {display "Linker script"flavor datano_definecalculated { "src/openrisc.ld" }}make {<PREFIX>/lib/target.ld: <PACKAGE>/src/openrisc.ld$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(ACTUAL_CFLAGS) -o $@ $<@echo $@ ": \\" > $(notdir $@).deps@tail -n +2 target.tmp >> $(notdir $@).deps@echo >> $(notdir $@).deps@rm target.tmp}cdl_component CYG_HAL_STARTUP {display "Startup type"flavor datalegal_values {"RAM" "ROM" "JTAG"}default_value {"JTAG"}no_definedefine -file system.h CYG_HAL_STARTUPdescription "Selects whether code initially runs from ROM or RAM. In the case of ROM startup,it's possible for the code to be copied into RAM and executed there."}cdl_component CYGHWR_MEMORY_LAYOUT {display "Memory layout"flavor datano_definecalculated { CYG_HAL_STARTUP == "ROM" ? "openrisc_orpsoc_rom" : \"openrisc_orpsoc_ram" }cdl_option CYGHWR_MEMORY_LAYOUT_LDI {display "Memory layout linker script fragment"flavor datano_definedefine -file system.h CYGHWR_MEMORY_LAYOUT_LDIcalculated { CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_openrisc_orpsoc_rom.ldi>" : \"<pkgconf/mlt_openrisc_orpsoc_ram.ldi>" }}cdl_option CYGHWR_MEMORY_LAYOUT_H {display "Memory layout header file"flavor datano_definedefine -file system.h CYGHWR_MEMORY_LAYOUT_Hcalculated { CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_openrisc_orpsoc_rom.h>" : \"<pkgconf/mlt_openrisc_orpsoc_ram.h>" }}}# Real-time clock/counter specificscdl_component CYGNUM_HAL_RTC_CONSTANTS {display "Real-time clock constants."flavor nonecdl_option CYGNUM_HAL_RTC_NUMERATOR {display "Real-time clock numerator"flavor datadefault_value 1000000000}cdl_option CYGNUM_HAL_RTC_DENOMINATOR {display "Real-time clock denominator"flavor datadefault_value 100}cdl_option CYGNUM_HAL_RTC_PERIOD {display "Real-time clock period"flavor datadefault_value {CYGHWR_HAL_OPENRISC_CPU_FREQ * 1000000 / CYGNUM_HAL_RTC_DENOMINATOR}description "The tick timer facility is usedto drive the eCos kernel RTC. The count registerincrements at the CPU clock speed. By default, 100 Hz"}}cdl_component CYGBLD_GLOBAL_OPTIONS {display "Global build options"flavor nonedescription "Global build options including control overcompiler flags, linker flags and choice of toolchain."parent CYGPKG_NONEcdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {display "Global command prefix"flavor datano_definedefault_value { "or32-elf" }description "This option specifies the command prefix used wheninvoking the build tools."}cdl_option CYGBLD_GLOBAL_CFLAGS {display "Global compiler flags"flavor datano_definedefault_value { CYGBLD_GLOBAL_WARNFLAGS ."-g -O2 -fno-omit-frame-pointer -fno-rtti -fno-exceptions " .(CYGHWR_MUL_IMPLEMENTED ? "-mhard-mul " : "-msoft-mul ") .(CYGHWR_DIV_IMPLEMENTED ? "-mhard-div " : "-msoft-div ") .(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") }description "This option controls the global compiler flags whichare used to compile all packages bydefault. Individual packages may defineoptions which override these global flags."}cdl_option CYGBLD_GLOBAL_LDFLAGS {display "Global linker flags"flavor datano_definedefault_value { "-g -O2 -nostdlib -Wl,--gc-sections -Wl,-static " .(CYGHWR_MUL_IMPLEMENTED ? "-mhard-mul " : "-msoft-mul ") .(CYGHWR_DIV_IMPLEMENTED ? "-mhard-div " : "-msoft-div ") .(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") }description "This option controls the global linker flags. Individualpackages may define options which override these global flags."}}cdl_option CYGBLD_BUILD_GDB_STUBS {display "Build GDB stub ROM image"default_value 0parent CYGBLD_GLOBAL_OPTIONSrequires { CYG_HAL_STARTUP == "ROM" }requires CYGSEM_HAL_ROM_MONITORrequires CYGBLD_BUILD_COMMON_GDB_STUBSrequires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBSrequires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORTrequires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORTrequires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXTrequires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUMno_definedescription "This option enables the building of the GDB stubs for theboard. The common HAL controls takes care of most of thebuild process, but the final conversion from ELF image tobinary data is handled by the platform CDL, allowingrelocation of the data if necessary."make -priority 320 {<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img$(OBJCOPY) -O binary $< $@}}cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {display "Number of breakpoints supported by the HAL."flavor datadefault_value 25description "This option determines the number of breakpoints supported by the HAL."}cdl_option CYGSEM_HAL_USE_ROM_MONITOR {display "Work with a ROM monitor"flavor booldefault_value { CYG_HAL_STARTUP == "RAM" ? 1 : 0 }parent CYGPKG_HAL_ROM_MONITORrequires { CYG_HAL_STARTUP == "RAM" }description "Allow coexistence with ROM monitor (CygMon or GDB stubs) byonly initializing interrupt vectors on startup, thus leavingexception handling to the ROM monitor."}cdl_option CYGSEM_HAL_ROM_MONITOR {display "Behave as a ROM monitor"flavor booldefault_value 0parent CYGPKG_HAL_ROM_MONITORrequires { CYG_HAL_STARTUP == "ROM" }description "Enable this option if this program is to be used as a ROM monitor,i.e. applications will be loaded into RAM on the board, and thisROM monitor may process exceptions or interrupts generated from theapplication. This enables features such as utilizing a separateinterrupt stack when exceptions are generated."}cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {display "Redboot HAL options"flavor noneno_defineparent CYGPKG_REDBOOTactive_if CYGPKG_REDBOOTdescription "This option lists the target's requirements for a valid Redbootconfiguration."cdl_option CYGBLD_BUILD_REDBOOT_BIN {display "Build Redboot ROM binary image"active_if CYGBLD_BUILD_REDBOOTdefault_value 1no_definedescription "This option enables the conversion of the Redboot ELFimage to a binary image suitable for ROM programming."compile -library=libextras.amake -priority 325 {<PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf$(OBJCOPY) --strip-all $< $(@:.srec=.img)$(OBJCOPY) -O srec $< $@}}}cdl_option CYGHWR_HAL_OPENRISC_CPU_FREQ {display "CPU frequency"flavor datalegal_values 0 to 1000000default_value 50description "This option contains the frequency of the CPU in MegaHertz.Choose the frequency to match the processor you have. Thismay affect thing like serial device, interval clock andmemory access speed settings."}cdl_option CYGHWR_MUL_IMPLEMENTED {display "Hardware multiplier implemented"flavor booldefault_value 1description "Select this option only if hardware multiplier isimplemented."}cdl_option CYGHWR_DIV_IMPLEMENTED {display "Hardware divisor implemented"flavor booldefault_value 1description "Select this option only if hardware division isimplemented."}cdl_option CYGHWR_FPU_IMPLEMENTED {display "Hardware FPU implemented"flavor booldefault_value 0description "Select this option only if FPU is implemented."}cdl_component CYGHWR_CACHE {display "Cache"flavor nonedescription "Cache is optional in the OpenRISC architecture. Removingcache is a common way to save hardware space."cdl_option CYGHWR_ICACHE_IMPLEMENTED {display "Instruction cache implemented"flavor booldefault_value 1description "Select this option only if instruction cache isimplemented."}cdl_option CYGHWR_ICACHE_SIZE {display "Instruction cache size"active_if CYGHWR_ICACHE_IMPLEMENTEDflavor datalegal_values 4096 8192default_value 8192description "Size of the instruction cache."}cdl_option CYGHWR_DCACHE_IMPLEMENTED {display "Data cache implemented"flavor booldefault_value 1description "Select this option only if data cache isimplemented."}cdl_option CYGHWR_DCACHE_SIZE {display "Data cache size"active_if CYGHWR_DCACHE_IMPLEMENTEDflavor datalegal_values 4096 8192default_value 4096description "Size of the data cache."}}}# EOF hal_openrisc.cdl
Go to most recent revision | Compare with Previous | Blame | View Log
