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//=============================================================================
//
//      mod_regs_intc.h
//
//      INTC (interrupt controller) Module register definitions
//
//=============================================================================
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// -------------------------------------------                              
// This file is part of eCos, the Embedded Configurable Operating System.   
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//
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//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   jskov
// Contributors:jskov, nickg
// Date:        2000-10-30
//              
//####DESCRIPTIONEND####
//
//=============================================================================
 
//--------------------------------------------------------------------------
// Interrupt registers, module type 1
 
#define CYGARC_REG_TRA                  0xFF000020
#define CYGARC_REG_EXCEVT               0xFF000024
#define CYGARC_REG_INTEVT               0xFF000028
 
#define CYGARC_REG_ICR                  0xFFD00000
#define CYGARC_REG_IPRA                 0xFFD00004
#define CYGARC_REG_IPRB                 0xFFD00008
#define CYGARC_REG_IPRC                 0xFFD0000C
 
#define CYGARC_REG_ICR_NMIL             0x8000
#define CYGARC_REG_ICR_MAI              0x4000
#define CYGARC_REG_ICR_NMIB             0x0200
#define CYGARC_REG_ICR_NMIE             0x0100
#define CYGARC_REG_ICR_IRLM             0x0080
#define CYGARC_REG_ICR_SRST             0x0001
 
#define CYGARC_REG_IPRA_TMU0_MASK       0xf000
#define CYGARC_REG_IPRA_TMU0_PRI1       0x1000
#define CYGARC_REG_IPRA_TMU1_MASK       0x0f00
#define CYGARC_REG_IPRA_TMU1_PRI1       0x0100
#define CYGARC_REG_IPRA_TMU2_MASK       0x00f0
#define CYGARC_REG_IPRA_TMU2_PRI1       0x0010
#define CYGARC_REG_IPRA_RTC_MASK        0x000f
#define CYGARC_REG_IPRA_RTC_PRI1        0x0001
 
#define CYGARC_REG_IPRB_WDT_MASK        0xf000
#define CYGARC_REG_IPRB_WDT_PRI1        0x1000
#define CYGARC_REG_IPRB_REF_MASK        0x0f00
#define CYGARC_REG_IPRB_REF_PRI1        0x0100
#define CYGARC_REG_IPRB_SCI_MASK        0x00f0
#define CYGARC_REG_IPRB_SCI_PRI1        0x0010
 
#define CYGARC_REG_IPRC_GPIO_MASK       0xF000
#define CYGARC_REG_IPRC_GPIO_PRI1       0x1000
#define CYGARC_REG_IPRC_DMAC_MASK       0x0F00
#define CYGARC_REG_IPRC_DMAC_PRI1       0x0100
#define CYGARC_REG_IPRC_SCIF_MASK       0x00F0
#define CYGARC_REG_IPRC_SCIF_PRI1       0x0010
#define CYGARC_REG_IPRC_HUDI_MASK       0x000F
#define CYGARC_REG_IPRC_HUDI_PRI1       0x0001
 
#if (CYGARC_SH_MOD_INTC == 2)
#define CYGARC_REG_IPRD                  0xffd00010
#define CYGARC_REG_INTPRI00              0xfe080000
#define CYGARC_REG_INTREQ00              0xfe080020
#define CYGARC_REG_INTMSK00              0xfe080040
#define CYGARC_REG_INTMSKCLR00           0xfe080060
 
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
#define CYGARC_REG_IPRD_IRL0_MASK        0xf000
#define CYGARC_REG_IPRD_IRL0_PRI1        0x1000
#define CYGARC_REG_IPRD_IRL1_MASK        0x0f00
#define CYGARC_REG_IPRD_IRL1_PRI1        0x0100
#define CYGARC_REG_IPRD_IRL2_MASK        0x00f0
#define CYGARC_REG_IPRD_IRL2_PRI1        0x0010
#define CYGARC_REG_IPRD_IRL3_MASK        0x000f
#define CYGARC_REG_IPRD_IRL3_PRI1        0x0001
#endif
 
#define CYGARC_REG_INTPRI00_PCISERR_MASK 0x0000000f
#define CYGARC_REG_INTPRI00_PCISERR_PRI1 0x00000001
#define CYGARC_REG_INTPRI00_PCIERR_MASK  0x000000f0
#define CYGARC_REG_INTPRI00_PCIERR_PRI1  0x00000010
#define CYGARC_REG_INTPRI00_TUNI3_MASK   0x00000f00
#define CYGARC_REG_INTPRI00_TUNI3_PRI1   0x00000100
#define CYGARC_REG_INTPRI00_TUNI4_MASK   0x0000f000
#define CYGARC_REG_INTPRI00_TUNI4_PRI1   0x00001000
 
#endif
 
// The (initial) IRQ mode is controlled by configuration.
#ifdef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
# define CYGARC_REG_ICR_INIT 0x0000
#else
# define CYGARC_REG_ICR_INIT (CYGARC_REG_ICR_IRLM)
#endif