URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [v85x/] [arch/] [current/] [include/] [hal_intr.h] - Rev 811
Go to most recent revision | Compare with Previous | Blame | View Log
#ifndef CYGONCE_HAL_HAL_INTR_H #define CYGONCE_HAL_HAL_INTR_H //========================================================================== // // hal_intr.h // // HAL Interrupt and clock support // //========================================================================== // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later // version. // // eCos is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License // along with eCos; if not, write to the Free Software Foundation, Inc., // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. // // As a special exception, if other files instantiate templates or use // macros or inline functions from this file, or you compile this file // and link it with other works to produce a work based on this file, // this file does not by itself cause the resulting work to be covered by // the GNU General Public License. However the source code for this file // must still be made available in accordance with section (3) of the GNU // General Public License v2. // // This exception does not invalidate any other reasons why a work based // on this file might be covered by the GNU General Public License. // ------------------------------------------- // ####ECOSGPLCOPYRIGHTEND#### //========================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): nickg // Contributors: nickg, jskov, // gthomas, jlarmour // Date: 1999-02-16 // Purpose: Define Interrupt support // Description: The macros defined here provide the HAL APIs for handling // interrupts and the clock. // // Usage: // #include <cyg/hal/hal_intr.h> // ... // // //####DESCRIPTIONEND#### // //========================================================================== #include <pkgconf/hal.h> #include <pkgconf/hal_v85x.h> #include <cyg/infra/cyg_type.h> #include <cyg/hal/hal_io.h> #include <cyg/hal/var_intr.h> //-------------------------------------------------------------------------- // Static data used by HAL // ISR tables externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; // VSR table externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; //-------------------------------------------------------------------------- // Default ISR // The #define is used to test whether this routine exists, and to allow // us to call it. externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); #define HAL_DEFAULT_ISR hal_default_isr //-------------------------------------------------------------------------- // Interrupt state storage typedef cyg_uint32 CYG_INTERRUPT_STATE; //-------------------------------------------------------------------------- // Interrupt control macros externC cyg_uint32 hal_disable_interrupts(void); externC void hal_enable_interrupts(void); externC void hal_restore_interrupts(cyg_uint32); externC cyg_uint32 hal_query_interrupts(void); #ifdef CYGSEM_HAL_NEC_INLINE_INTERRUPT_FUNCTIONS #define HAL_DISABLE_INTERRUPTS(_old_) \ CYG_MACRO_START \ asm volatile ( \ "stsr PSW,%0;" \ "di" \ : "=r"(_old_)); \ CYG_MACRO_END #define HAL_ENABLE_INTERRUPTS() \ CYG_MACRO_START \ asm volatile ( \ "ei" \ : ); \ CYG_MACRO_END #define HAL_RESTORE_INTERRUPTS(_old_) \ CYG_MACRO_START \ asm volatile ( \ "ldsr %0,PSW" \ : \ : "r" (_old_)); \ CYG_MACRO_END #else #define HAL_DISABLE_INTERRUPTS(_old_) _old_ = hal_disable_interrupts() #define HAL_ENABLE_INTERRUPTS() hal_enable_interrupts() #define HAL_RESTORE_INTERRUPTS(_old_) hal_restore_interrupts(_old_) #endif #define HAL_QUERY_INTERRUPTS( _state_ ) _state_ = hal_query_interrupts() //-------------------------------------------------------------------------- // Routine to execute DSRs using separate interrupt stack #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK externC void hal_interrupt_stack_call_pending_DSRs(void); #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ hal_interrupt_stack_call_pending_DSRs() // these are offered solely for stack usage testing // if they are not defined, then there is no interrupt stack. #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack // use them to declare these extern however you want: // extern char HAL_INTERRUPT_STACK_BASE[]; // extern char HAL_INTERRUPT_STACK_TOP[]; // is recommended #endif //-------------------------------------------------------------------------- // Vector translation. // For chained interrupts we only have a single vector though which all // are passed. For unchained interrupts we have a vector per interrupt. // Note: this hardware does not have/support chained interrupts. //-------------------------------------------------------------------------- // Vector translation. // For chained interrupts we only have a single vector though which all // are passed. For unchained interrupts we have a vector per interrupt. #ifndef HAL_TRANSLATE_VECTOR #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 #else #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_-CYGNUM_HAL_ISR_MIN) #endif #endif #ifndef HAL_TRANSLATE_VECTOR #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_-CYGNUM_HAL_ISR_MIN) #endif //-------------------------------------------------------------------------- // Interrupt and VSR attachment macros #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ CYG_MACRO_START \ cyg_uint32 _index_; \ HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ \ if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ (_state_) = 0; \ else \ (_state_) = 1; \ CYG_MACRO_END #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ { \ cyg_uint32 _index_; \ HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ \ if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ { \ hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ } \ } #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ { \ cyg_uint32 _index_; \ HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ \ if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ { \ hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \ hal_interrupt_data[_index_] = 0; \ hal_interrupt_objects[_index_] = 0; \ } \ } #define HAL_VSR_GET( _vector_, _pvsr_ ) \ *(_pvsr_) = (void (*)())hal_vsr_table[_vector_]; #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \ if( _poldvsr_ != NULL) \ *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \ hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ CYG_MACRO_END // This is an ugly name, but what it means is: grab the VSR back to eCos // internal handling, or if you like, the default handler. But if // cooperating with GDB and CygMon, the default behaviour is to pass most // exceptions to CygMon. This macro undoes that so that eCos handles the // exception. So use it with care. externC void __default_exception_vsr(void); externC void __default_interrupt_vsr(void); #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \ HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \ ? (CYG_ADDRESS)__default_interrupt_vsr \ : (CYG_ADDRESS)__default_exception_vsr, \ _poldvsr_ ); \ CYG_MACRO_END //-------------------------------------------------------------------------- // Interrupt controller access externC void hal_interrupt_mask(int); externC void hal_interrupt_unmask(int); externC void hal_interrupt_acknowledge(int); #define HAL_INTERRUPT_MASK( _vector_ ) hal_interrupt_mask(_vector_) #define HAL_INTERRUPT_UNMASK( _vector_ ) hal_interrupt_unmask(_vector_) #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) hal_interrupt_acknowledge(_vector_) #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) //-------------------------------------------------------------------------- // Clock control. externC CYG_WORD32 cyg_hal_clock_period; externC void hal_clock_initialize(cyg_int32); externC void hal_clock_reset(int, cyg_uint32); externC cyg_uint32 hal_clock_read(void); #define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize(_period_) #define HAL_CLOCK_RESET( _vector_, _period_ ) hal_clock_reset(_vector_,_period_) #define HAL_CLOCK_READ( _pvalue_ ) *(_pvalue_) = hal_clock_read() #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ !defined(HAL_CLOCK_LATENCY) #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_) #endif //-------------------------------------------------------------------------- // Reset. #ifndef HAL_PLATFORM_RESET extern void hal_reset_board(void); #define HAL_PLATFORM_RESET() hal_reset_board() #define HAL_PLATFORM_RESET_ENTRY 0x00000000 #endif //-------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_HAL_INTR_H // End of hal_intr.h
Go to most recent revision | Compare with Previous | Blame | View Log