OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_LPC2106_GCC/] [lpc2106-rom.ld] - Rev 675

Go to most recent revision | Compare with Previous | Blame | View Log

MEMORY 
{
        flash   : ORIGIN = 0, LENGTH = 120K
        ram             : ORIGIN = 0x40000000, LENGTH = 64K
}

__stack_end__ = 0x40000000 + 64K - 4;

SECTIONS 
{
        . = 0;
        startup : { *(.startup)} >flash

        prog : 
        {
                *(.text)
                *(.rodata)
                *(.rodata*)
                *(.glue_7)
                *(.glue_7t)
        } >flash

        __end_of_text__ = .;

        .data : 
        {
                __data_beg__ = .;
                __data_beg_src__ = __end_of_text__;
                *(.data)
                __data_end__ = .;
        } >ram AT>flash

        .bss : 
        {
                __bss_beg__ = .;
                *(.bss)
        } >ram

        . = ALIGN(4);
        .eh_frame :
        {
                 KEEP (*(.eh_frame))
        } > ram
        
        /* Align here to ensure that the .bss section occupies space up to
        _end.  Align after .bss to ensure correct alignment even if the
        .bss section disappears because there are no input sections.  */
        . = ALIGN(32 / 8);
}
        . = ALIGN(32 / 8);
        _end = .;
        _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
        PROVIDE (end = .);


Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.