OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cfg/] [MCF52259_INTERNAL_FLASH.cfg] - Rev 598

Go to most recent revision | Compare with Previous | Blame | View Log

ResetHalt

; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000

; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021

; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061

; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.