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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [cfg/] [mcf5225xEVB_PnE.cfg] - Rev 597

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ResetHalt

; Set VBR to the beginning of what will be SRAM
; VBR is an absolute CPU register
writecontrolreg 0x0801 0x20000000

; Set RAMBAR1 (SRAM)
writecontrolreg 0x0C05 0x20000021

; Set FLASHBAR (Flash)
writecontrolreg 0x0C04 0x00000061

; Enable PST[3:0] signals
writemem.b 0x40100074 0x0F

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