OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [Common/] [ethernet/] [lwIP_130/] [contrib/] [port/] [FreeRTOS/] [ColdFire/] [arch/] [cc.h] - Rev 606

Compare with Previous | Blame | View Log

/*
 * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 *
 * This file is part of the lwIP TCP/IP stack.
 *
 * Author: Adam Dunkels <adam@sics.se>
 * Modifcations: Christian Walter <wolti@sil.at>
 */
#ifndef __CC_H__
#define __CC_H__
 
/* ------------------------ System includes ------------------------------- */
 
/* ------------------------ Project includes ------------------------------ */
#include "cpu.h"
#include "sys_arch.h"
 
/* ------------------------ Defines --------------------------------------- */
 
//#pragma options align= packed
#define PACK_STRUCT_BEGIN		
#define PACK_STRUCT_STRUCT      //non CW compatible: __attribute__ ((__packed__))
#define PACK_STRUCT_END
 
#define PACK_STRUCT_FIELD( x )  x
 
/*FSL: non used on code:
#define ALIGN_STRUCT_8_BEGIN
#define ALIGN_STRUCT_8          //non CW compatible: __attribute__ ((aligned (8)))
#define ALIGN_STRUCT_8_END
*/
 
#define LWIP_PLATFORM_ASSERT( x ) sys_assert( x )
#define LWIP_PLATFORM_DIAG( x, ... ) do{ sys_debug x; } while( 0 );
 
/* Define (sn)printf formatters for these lwIP types */
#define U16_F                   "hu"
#define S16_F                   "hd"
#define X16_F                   "hx"
#define U32_F                   "lu"
#define S32_F                   "ld"
#define X32_F                   "lx"
 
/* ------------------------ Type definitions (lwIP) ----------------------- */
typedef unsigned char u8_t;
typedef signed char s8_t;
typedef unsigned short u16_t;
typedef signed short s16_t;
typedef unsigned long u32_t;
typedef signed long s32_t;
typedef u32_t   mem_ptr_t;
typedef int     sys_prot_t;
 
/* ------------------------ Prototypes ------------------------------------ */
 
#endif
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.