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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [HCS12_CodeWarrior_small/] [CODE/] [IO_Map.H] - Rev 800
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/** ###################################################################** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.** Filename : IO_Map.H** Project : RTOSDemo** Processor : MC9S12C32CFU** Beantype : IO_Map** Version : Driver 01.01** Compiler : Metrowerks HC12 C Compiler** Date/Time : 10/05/2005, 11:11** Abstract :** This bean "IO_Map" implements an IO devices mapping.** Settings :**** Contents :** No public methods**** (c) Copyright UNIS, spol. s r.o. 1997-2002** UNIS, spol. s r.o.** Jundrovska 33** 624 00 Brno** Czech Republic** http : www.processorexpert.com** mail : info@processorexpert.com** ###################################################################*//* Linker pragmas */#pragma LINK_INFO DERIVATIVE "MC9S12C32"#pragma LINK_INFO OSCFREQUENCY "16000000"#define REG_BASE 0x0000 /* Base address for the I/O register block *//* Based on CPU DB MC9S12C32_80, version 2.87.264 (RegistersPrg V1.027) */#ifndef _MC9S12C32_80_H#define _MC9S12C32_80_H#include "PE_Types.h"#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type *//*********************************************//* *//* PE I/O map format *//* *//*********************************************//*** PORTAB - Port AB Register; 0x00000000 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PORTA - Port A Register; 0x00000000 ***/union {byte Byte;struct {byte BIT0 :1; /* Port A Bit 0 */byte BIT1 :1; /* Port A Bit 1 */byte BIT2 :1; /* Port A Bit 2 */byte BIT3 :1; /* Port A Bit 3 */byte BIT4 :1; /* Port A Bit 4 */byte BIT5 :1; /* Port A Bit 5 */byte BIT6 :1; /* Port A Bit 6 */byte BIT7 :1; /* Port A Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} PORTASTR;#define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte#define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0#define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1#define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2#define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3#define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4#define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5#define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6#define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7#define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT/*** PORTB - Port B Register; 0x00000001 ***/union {byte Byte;struct {byte BIT0 :1; /* Port B Bit 0 */byte BIT1 :1; /* Port B Bit 1 */byte BIT2 :1; /* Port B Bit 2 */byte BIT3 :1; /* Port B Bit 3 */byte BIT4 :1; /* Port B Bit 4 */byte BIT5 :1; /* Port B Bit 5 */byte BIT6 :1; /* Port B Bit 6 */byte BIT7 :1; /* Port B Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} PORTBSTR;#define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte#define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0#define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1#define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2#define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3#define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4#define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5#define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6#define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7#define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT} Overlap_STR;struct {word BIT0 :1; /* Port AB Bit 0 */word BIT1 :1; /* Port AB Bit 1 */word BIT2 :1; /* Port AB Bit 2 */word BIT3 :1; /* Port AB Bit 3 */word BIT4 :1; /* Port AB Bit 4 */word BIT5 :1; /* Port AB Bit 5 */word BIT6 :1; /* Port AB Bit 6 */word BIT7 :1; /* Port AB Bit 7 */word BIT8 :1; /* Port AB Bit 8 */word BIT9 :1; /* Port AB Bit 9 */word BIT10 :1; /* Port AB Bit 10 */word BIT11 :1; /* Port AB Bit 11 */word BIT12 :1; /* Port AB Bit 12 */word BIT13 :1; /* Port AB Bit 13 */word BIT14 :1; /* Port AB Bit 14 */word BIT15 :1; /* Port AB Bit 15 */} Bits;struct {word grpBIT :16;} MergedBits;} PORTABSTR;extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);#define PORTAB _PORTAB.Word#define PORTAB_BIT0 _PORTAB.Bits.BIT0#define PORTAB_BIT1 _PORTAB.Bits.BIT1#define PORTAB_BIT2 _PORTAB.Bits.BIT2#define PORTAB_BIT3 _PORTAB.Bits.BIT3#define PORTAB_BIT4 _PORTAB.Bits.BIT4#define PORTAB_BIT5 _PORTAB.Bits.BIT5#define PORTAB_BIT6 _PORTAB.Bits.BIT6#define PORTAB_BIT7 _PORTAB.Bits.BIT7#define PORTAB_BIT8 _PORTAB.Bits.BIT8#define PORTAB_BIT9 _PORTAB.Bits.BIT9#define PORTAB_BIT10 _PORTAB.Bits.BIT10#define PORTAB_BIT11 _PORTAB.Bits.BIT11#define PORTAB_BIT12 _PORTAB.Bits.BIT12#define PORTAB_BIT13 _PORTAB.Bits.BIT13#define PORTAB_BIT14 _PORTAB.Bits.BIT14#define PORTAB_BIT15 _PORTAB.Bits.BIT15#define PORTAB_BIT _PORTAB.MergedBits.grpBIT/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** DDRA - Port A Data Direction Register; 0x00000002 ***/union {byte Byte;struct {byte BIT0 :1; /* Data Direction Port A Bit 0 */byte BIT1 :1; /* Data Direction Port A Bit 1 */byte BIT2 :1; /* Data Direction Port A Bit 2 */byte BIT3 :1; /* Data Direction Port A Bit 3 */byte BIT4 :1; /* Data Direction Port A Bit 4 */byte BIT5 :1; /* Data Direction Port A Bit 5 */byte BIT6 :1; /* Data Direction Port A Bit 6 */byte BIT7 :1; /* Data Direction Port A Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} DDRASTR;#define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte#define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0#define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1#define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2#define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3#define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4#define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5#define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6#define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7#define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT/*** DDRB - Port B Data Direction Register; 0x00000003 ***/union {byte Byte;struct {byte BIT0 :1; /* Data Direction Port B Bit 0 */byte BIT1 :1; /* Data Direction Port B Bit 1 */byte BIT2 :1; /* Data Direction Port B Bit 2 */byte BIT3 :1; /* Data Direction Port B Bit 3 */byte BIT4 :1; /* Data Direction Port B Bit 4 */byte BIT5 :1; /* Data Direction Port B Bit 5 */byte BIT6 :1; /* Data Direction Port B Bit 6 */byte BIT7 :1; /* Data Direction Port B Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} DDRBSTR;#define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte#define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0#define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1#define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2#define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3#define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4#define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5#define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6#define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7#define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT} Overlap_STR;struct {word BIT0 :1; /* Data Direction Port B Bit 0 */word BIT1 :1; /* Data Direction Port B Bit 1 */word BIT2 :1; /* Data Direction Port B Bit 2 */word BIT3 :1; /* Data Direction Port B Bit 3 */word BIT4 :1; /* Data Direction Port B Bit 4 */word BIT5 :1; /* Data Direction Port B Bit 5 */word BIT6 :1; /* Data Direction Port B Bit 6 */word BIT7 :1; /* Data Direction Port B Bit 7 */word BIT8 :1; /* Data Direction Port A Bit 8 */word BIT9 :1; /* Data Direction Port A Bit 9 */word BIT10 :1; /* Data Direction Port A Bit 10 */word BIT11 :1; /* Data Direction Port A Bit 11 */word BIT12 :1; /* Data Direction Port A Bit 12 */word BIT13 :1; /* Data Direction Port A Bit 13 */word BIT14 :1; /* Data Direction Port A Bit 14 */word BIT15 :1; /* Data Direction Port A Bit 15 */} Bits;struct {word grpBIT :16;} MergedBits;} DDRABSTR;extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);#define DDRAB _DDRAB.Word#define DDRAB_BIT0 _DDRAB.Bits.BIT0#define DDRAB_BIT1 _DDRAB.Bits.BIT1#define DDRAB_BIT2 _DDRAB.Bits.BIT2#define DDRAB_BIT3 _DDRAB.Bits.BIT3#define DDRAB_BIT4 _DDRAB.Bits.BIT4#define DDRAB_BIT5 _DDRAB.Bits.BIT5#define DDRAB_BIT6 _DDRAB.Bits.BIT6#define DDRAB_BIT7 _DDRAB.Bits.BIT7#define DDRAB_BIT8 _DDRAB.Bits.BIT8#define DDRAB_BIT9 _DDRAB.Bits.BIT9#define DDRAB_BIT10 _DDRAB.Bits.BIT10#define DDRAB_BIT11 _DDRAB.Bits.BIT11#define DDRAB_BIT12 _DDRAB.Bits.BIT12#define DDRAB_BIT13 _DDRAB.Bits.BIT13#define DDRAB_BIT14 _DDRAB.Bits.BIT14#define DDRAB_BIT15 _DDRAB.Bits.BIT15#define DDRAB_BIT _DDRAB.MergedBits.grpBIT/*** TCNT - Timer Count Register; 0x00000044 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TCNTHi - Timer Count Register High; 0x00000044 ***/union {byte Byte;struct {byte BIT15 :1; /* Timer Count Register Bit 15 */byte BIT14 :1; /* Timer Count Register Bit 14 */byte BIT13 :1; /* Timer Count Register Bit 13 */byte BIT12 :1; /* Timer Count Register Bit 12 */byte BIT11 :1; /* Timer Count Register Bit 11 */byte BIT10 :1; /* Timer Count Register Bit 10 */byte BIT9 :1; /* Timer Count Register Bit 9 */byte BIT8 :1; /* Timer Count Register Bit 8 */} Bits;} TCNTHiSTR;#define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte#define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15#define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14#define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13#define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12#define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11#define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10#define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9#define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8/*** TCNTLo - Timer Count Register Low; 0x00000045 ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Count Register Bit 0 */byte BIT1 :1; /* Timer Count Register Bit 1 */byte BIT2 :1; /* Timer Count Register Bit 2 */byte BIT3 :1; /* Timer Count Register Bit 3 */byte BIT4 :1; /* Timer Count Bit Register 4 */byte BIT5 :1; /* Timer Count Bit Register 5 */byte BIT6 :1; /* Timer Count Bit Register 6 */byte BIT7 :1; /* Timer Count Bit Register 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TCNTLoSTR;#define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte#define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0#define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1#define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2#define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3#define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4#define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5#define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6#define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7#define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TCNTSTR;extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);#define TCNT _TCNT.Word#define TCNT_BIT _TCNT.MergedBits.grpBIT/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC0HiSTR;#define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte#define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8#define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9#define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10#define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11#define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12#define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13#define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14#define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15#define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8#define TC0Hi_BIT TC0Hi_BIT_8/*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC0LoSTR;#define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte#define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0#define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1#define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2#define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3#define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4#define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5#define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6#define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7#define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC0STR;extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);#define TC0 _TC0.Word#define TC0_BIT _TC0.MergedBits.grpBIT/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC1HiSTR;#define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte#define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8#define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9#define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10#define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11#define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12#define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13#define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14#define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15#define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8#define TC1Hi_BIT TC1Hi_BIT_8/*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC1LoSTR;#define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte#define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0#define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1#define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2#define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3#define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4#define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5#define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6#define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7#define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC1STR;extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);#define TC1 _TC1.Word#define TC1_BIT _TC1.MergedBits.grpBIT/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC2HiSTR;#define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte#define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8#define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9#define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10#define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11#define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12#define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13#define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14#define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15#define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8#define TC2Hi_BIT TC2Hi_BIT_8/*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC2LoSTR;#define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte#define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0#define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1#define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2#define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3#define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4#define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5#define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6#define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7#define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC2STR;extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);#define TC2 _TC2.Word#define TC2_BIT _TC2.MergedBits.grpBIT/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC3HiSTR;#define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte#define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8#define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9#define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10#define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11#define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12#define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13#define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14#define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15#define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8#define TC3Hi_BIT TC3Hi_BIT_8/*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC3LoSTR;#define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte#define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0#define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1#define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2#define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3#define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4#define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5#define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6#define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7#define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC3STR;extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);#define TC3 _TC3.Word#define TC3_BIT _TC3.MergedBits.grpBIT/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC4HiSTR;#define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte#define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8#define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9#define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10#define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11#define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12#define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13#define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14#define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15#define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8#define TC4Hi_BIT TC4Hi_BIT_8/*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC4LoSTR;#define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte#define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0#define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1#define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2#define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3#define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4#define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5#define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6#define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7#define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC4STR;extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);#define TC4 _TC4.Word#define TC4_BIT _TC4.MergedBits.grpBIT/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC5HiSTR;#define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte#define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8#define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9#define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10#define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11#define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12#define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13#define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14#define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15#define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8#define TC5Hi_BIT TC5Hi_BIT_8/*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC5LoSTR;#define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte#define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0#define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1#define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2#define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3#define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4#define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5#define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6#define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7#define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC5STR;extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);#define TC5 _TC5.Word#define TC5_BIT _TC5.MergedBits.grpBIT/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC6HiSTR;#define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte#define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8#define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9#define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10#define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11#define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12#define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13#define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14#define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15#define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8#define TC6Hi_BIT TC6Hi_BIT_8/*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC6LoSTR;#define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte#define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0#define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1#define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2#define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3#define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4#define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5#define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6#define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7#define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC6STR;extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);#define TC6 _TC6.Word#define TC6_BIT _TC6.MergedBits.grpBIT/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/typedef union {word Word;/* Overlapped registers: */struct {/*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/union {byte Byte;struct {byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} TC7HiSTR;#define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte#define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8#define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9#define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10#define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11#define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12#define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13#define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14#define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15#define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8#define TC7Hi_BIT TC7Hi_BIT_8/*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/union {byte Byte;struct {byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} TC7LoSTR;#define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte#define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0#define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1#define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2#define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3#define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4#define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5#define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6#define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7#define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} TC7STR;extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);#define TC7 _TC7.Word#define TC7_BIT _TC7.MergedBits.grpBIT/*** PACNT - Pulse Accumulators Count Register; 0x00000062 ***/typedef union {word Word;struct {word grpBIT :16;} MergedBits;} PACNTSTR;extern volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062);#define PACNT _PACNT.Word#define PACNT_BIT _PACNT.MergedBits.grpBIT/*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***/union {byte Byte;struct {byte ASCIF :1; /* ATD Sequence Complete Interrupt Flag */byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */byte ETRIGE :1; /* External Trigger Mode enable */byte ETRIGP :1; /* External Trigger Polarity */byte ETRIGLE :1; /* External Trigger Level/Edge control */byte AWAI :1; /* ATD Wait Mode */byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */byte ADPU :1; /* ATD Disable / Power Down */} Bits;} ATDCTL2STR;#define ATDCTL2 _ATDCTL23.Overlap_STR.ATDCTL2STR.Byte#define ATDCTL2_ASCIF _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIF#define ATDCTL2_ASCIE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIE#define ATDCTL2_ETRIGE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGE#define ATDCTL2_ETRIGP _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGP#define ATDCTL2_ETRIGLE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGLE#define ATDCTL2_AWAI _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AWAI#define ATDCTL2_AFFC _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AFFC#define ATDCTL2_ADPU _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ADPU/*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***/union {byte Byte;struct {byte FRZ0 :1; /* Background Debug Freeze Enable */byte FRZ1 :1; /* Background Debug Freeze Enable */byte FIFO :1; /* Result Register FIFO Mode */byte S1C :1; /* Conversion Sequence Length 1 */byte S2C :1; /* Conversion Sequence Length 2 */byte S4C :1; /* Conversion Sequence Length 4 */byte S8C :1; /* Conversion Sequence Length 8 */byte :1;} Bits;struct {byte grpFRZ :2;byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} ATDCTL3STR;#define ATDCTL3 _ATDCTL23.Overlap_STR.ATDCTL3STR.Byte#define ATDCTL3_FRZ0 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ0#define ATDCTL3_FRZ1 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ1#define ATDCTL3_FIFO _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FIFO#define ATDCTL3_S1C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S1C#define ATDCTL3_S2C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S2C#define ATDCTL3_S4C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S4C#define ATDCTL3_S8C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S8C#define ATDCTL3_FRZ _ATDCTL23.Overlap_STR.ATDCTL3STR.MergedBits.grpFRZ} Overlap_STR;struct {word FRZ0 :1; /* Background Debug Freeze Enable */word FRZ1 :1; /* Background Debug Freeze Enable */word FIFO :1; /* Result Register FIFO Mode */word S1C :1; /* Conversion Sequence Length 1 */word S2C :1; /* Conversion Sequence Length 2 */word S4C :1; /* Conversion Sequence Length 4 */word S8C :1; /* Conversion Sequence Length 8 */word :1;word ASCIF :1; /* ATD Sequence Complete Interrupt Flag */word ASCIE :1; /* ATD Sequence Complete Interrupt Enable */word ETRIGE :1; /* External Trigger Mode enable */word ETRIGP :1; /* External Trigger Polarity */word ETRIGLE :1; /* External Trigger Level/Edge control */word AWAI :1; /* ATD Wait Mode */word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */word ADPU :1; /* ATD Disable / Power Down */} Bits;struct {word grpFRZ :2;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;} MergedBits;} ATDCTL23STR;extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082);#define ATDCTL23 _ATDCTL23.Word#define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0#define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1#define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO#define ATDCTL23_S1C _ATDCTL23.Bits.S1C#define ATDCTL23_S2C _ATDCTL23.Bits.S2C#define ATDCTL23_S4C _ATDCTL23.Bits.S4C#define ATDCTL23_S8C _ATDCTL23.Bits.S8C#define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF#define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE#define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE#define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP#define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE#define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI#define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC#define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU#define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ/*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/union {byte Byte;struct {byte PRS0 :1; /* ATD Clock Prescaler 0 */byte PRS1 :1; /* ATD Clock Prescaler 1 */byte PRS2 :1; /* ATD Clock Prescaler 2 */byte PRS3 :1; /* ATD Clock Prescaler 3 */byte PRS4 :1; /* ATD Clock Prescaler 4 */byte SMP0 :1; /* Sample Time Select 0 */byte SMP1 :1; /* Sample Time Select 1 */byte SRES8 :1; /* A/D Resolution Select */} Bits;struct {byte grpPRS :5;byte grpSMP :2;byte grpSRES_8 :1;} MergedBits;} ATDCTL4STR;#define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte#define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0#define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1#define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2#define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3#define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4#define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0#define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1#define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8#define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS#define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP/*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/union {byte Byte;struct {byte CA :1; /* Analog Input Channel Select Code A */byte CB :1; /* Analog Input Channel Select Code B */byte CC :1; /* Analog Input Channel Select Code C */byte :1;byte MULT :1; /* Multi-Channel Sample Mode */byte SCAN :1; /* Continuous Conversion Sequence Mode */byte DSGN :1; /* Signed/Unsigned Result Data Mode */byte DJM :1; /* Result Register Data Justification Mode */} Bits;} ATDCTL5STR;#define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte#define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA#define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB#define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC#define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT#define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN#define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN#define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM} Overlap_STR;struct {word CA :1; /* Analog Input Channel Select Code A */word CB :1; /* Analog Input Channel Select Code B */word CC :1; /* Analog Input Channel Select Code C */word :1;word MULT :1; /* Multi-Channel Sample Mode */word SCAN :1; /* Continuous Conversion Sequence Mode */word DSGN :1; /* Signed/Unsigned Result Data Mode */word DJM :1; /* Result Register Data Justification Mode */word PRS0 :1; /* ATD Clock Prescaler 0 */word PRS1 :1; /* ATD Clock Prescaler 1 */word PRS2 :1; /* ATD Clock Prescaler 2 */word PRS3 :1; /* ATD Clock Prescaler 3 */word PRS4 :1; /* ATD Clock Prescaler 4 */word SMP0 :1; /* Sample Time Select 0 */word SMP1 :1; /* Sample Time Select 1 */word SRES8 :1; /* A/D Resolution Select */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word :1;word :1;word grpPRS :5;word grpSMP :2;word grpSRES_8 :1;} MergedBits;} ATDCTL45STR;extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084);#define ATDCTL45 _ATDCTL45.Word#define ATDCTL45_CA _ATDCTL45.Bits.CA#define ATDCTL45_CB _ATDCTL45.Bits.CB#define ATDCTL45_CC _ATDCTL45.Bits.CC#define ATDCTL45_MULT _ATDCTL45.Bits.MULT#define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN#define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN#define ATDCTL45_DJM _ATDCTL45.Bits.DJM#define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0#define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1#define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2#define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3#define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4#define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0#define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1#define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8#define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS#define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP/*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR0HSTR;#define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte#define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8#define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9#define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10#define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11#define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12#define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13#define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14#define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15#define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8#define ATDDR0H_BIT ATDDR0H_BIT_8/*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR0LSTR;#define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte#define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6#define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7#define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6#define ATDDR0L_BIT ATDDR0L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR0STR;extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090);#define ATDDR0 _ATDDR0.Word#define ATDDR0_BIT6 _ATDDR0.Bits.BIT6#define ATDDR0_BIT7 _ATDDR0.Bits.BIT7#define ATDDR0_BIT8 _ATDDR0.Bits.BIT8#define ATDDR0_BIT9 _ATDDR0.Bits.BIT9#define ATDDR0_BIT10 _ATDDR0.Bits.BIT10#define ATDDR0_BIT11 _ATDDR0.Bits.BIT11#define ATDDR0_BIT12 _ATDDR0.Bits.BIT12#define ATDDR0_BIT13 _ATDDR0.Bits.BIT13#define ATDDR0_BIT14 _ATDDR0.Bits.BIT14#define ATDDR0_BIT15 _ATDDR0.Bits.BIT15#define ATDDR0_BIT_6 _ATDDR0.MergedBits.grpBIT_6#define ATDDR0_BIT ATDDR0_BIT_6/*** ATDDR1 - A/D Conversion Result Register 1; 0x00000092 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR1H - A/D Conversion Result Register 1 High; 0x00000092 ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR1HSTR;#define ATDDR1H _ATDDR1.Overlap_STR.ATDDR1HSTR.Byte#define ATDDR1H_BIT8 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT8#define ATDDR1H_BIT9 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT9#define ATDDR1H_BIT10 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT10#define ATDDR1H_BIT11 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT11#define ATDDR1H_BIT12 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT12#define ATDDR1H_BIT13 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT13#define ATDDR1H_BIT14 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT14#define ATDDR1H_BIT15 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT15#define ATDDR1H_BIT_8 _ATDDR1.Overlap_STR.ATDDR1HSTR.MergedBits.grpBIT_8#define ATDDR1H_BIT ATDDR1H_BIT_8/*** ATDDR1L - A/D Conversion Result Register 1 Low; 0x00000093 ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR1LSTR;#define ATDDR1L _ATDDR1.Overlap_STR.ATDDR1LSTR.Byte#define ATDDR1L_BIT6 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT6#define ATDDR1L_BIT7 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT7#define ATDDR1L_BIT_6 _ATDDR1.Overlap_STR.ATDDR1LSTR.MergedBits.grpBIT_6#define ATDDR1L_BIT ATDDR1L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR1STR;extern volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092);#define ATDDR1 _ATDDR1.Word#define ATDDR1_BIT6 _ATDDR1.Bits.BIT6#define ATDDR1_BIT7 _ATDDR1.Bits.BIT7#define ATDDR1_BIT8 _ATDDR1.Bits.BIT8#define ATDDR1_BIT9 _ATDDR1.Bits.BIT9#define ATDDR1_BIT10 _ATDDR1.Bits.BIT10#define ATDDR1_BIT11 _ATDDR1.Bits.BIT11#define ATDDR1_BIT12 _ATDDR1.Bits.BIT12#define ATDDR1_BIT13 _ATDDR1.Bits.BIT13#define ATDDR1_BIT14 _ATDDR1.Bits.BIT14#define ATDDR1_BIT15 _ATDDR1.Bits.BIT15#define ATDDR1_BIT_6 _ATDDR1.MergedBits.grpBIT_6#define ATDDR1_BIT ATDDR1_BIT_6/*** ATDDR2 - A/D Conversion Result Register 2; 0x00000094 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR2H - A/D Conversion Result Register 2 High; 0x00000094 ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR2HSTR;#define ATDDR2H _ATDDR2.Overlap_STR.ATDDR2HSTR.Byte#define ATDDR2H_BIT8 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT8#define ATDDR2H_BIT9 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT9#define ATDDR2H_BIT10 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT10#define ATDDR2H_BIT11 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT11#define ATDDR2H_BIT12 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT12#define ATDDR2H_BIT13 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT13#define ATDDR2H_BIT14 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT14#define ATDDR2H_BIT15 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT15#define ATDDR2H_BIT_8 _ATDDR2.Overlap_STR.ATDDR2HSTR.MergedBits.grpBIT_8#define ATDDR2H_BIT ATDDR2H_BIT_8/*** ATDDR2L - A/D Conversion Result Register 2 Low; 0x00000095 ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR2LSTR;#define ATDDR2L _ATDDR2.Overlap_STR.ATDDR2LSTR.Byte#define ATDDR2L_BIT6 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT6#define ATDDR2L_BIT7 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT7#define ATDDR2L_BIT_6 _ATDDR2.Overlap_STR.ATDDR2LSTR.MergedBits.grpBIT_6#define ATDDR2L_BIT ATDDR2L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR2STR;extern volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094);#define ATDDR2 _ATDDR2.Word#define ATDDR2_BIT6 _ATDDR2.Bits.BIT6#define ATDDR2_BIT7 _ATDDR2.Bits.BIT7#define ATDDR2_BIT8 _ATDDR2.Bits.BIT8#define ATDDR2_BIT9 _ATDDR2.Bits.BIT9#define ATDDR2_BIT10 _ATDDR2.Bits.BIT10#define ATDDR2_BIT11 _ATDDR2.Bits.BIT11#define ATDDR2_BIT12 _ATDDR2.Bits.BIT12#define ATDDR2_BIT13 _ATDDR2.Bits.BIT13#define ATDDR2_BIT14 _ATDDR2.Bits.BIT14#define ATDDR2_BIT15 _ATDDR2.Bits.BIT15#define ATDDR2_BIT_6 _ATDDR2.MergedBits.grpBIT_6#define ATDDR2_BIT ATDDR2_BIT_6/*** ATDDR3 - A/D Conversion Result Register 3; 0x00000096 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR3H - A/D Conversion Result Register 3 High; 0x00000096 ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR3HSTR;#define ATDDR3H _ATDDR3.Overlap_STR.ATDDR3HSTR.Byte#define ATDDR3H_BIT8 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT8#define ATDDR3H_BIT9 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT9#define ATDDR3H_BIT10 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT10#define ATDDR3H_BIT11 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT11#define ATDDR3H_BIT12 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT12#define ATDDR3H_BIT13 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT13#define ATDDR3H_BIT14 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT14#define ATDDR3H_BIT15 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT15#define ATDDR3H_BIT_8 _ATDDR3.Overlap_STR.ATDDR3HSTR.MergedBits.grpBIT_8#define ATDDR3H_BIT ATDDR3H_BIT_8/*** ATDDR3L - A/D Conversion Result Register 3 Low; 0x00000097 ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR3LSTR;#define ATDDR3L _ATDDR3.Overlap_STR.ATDDR3LSTR.Byte#define ATDDR3L_BIT6 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT6#define ATDDR3L_BIT7 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT7#define ATDDR3L_BIT_6 _ATDDR3.Overlap_STR.ATDDR3LSTR.MergedBits.grpBIT_6#define ATDDR3L_BIT ATDDR3L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR3STR;extern volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096);#define ATDDR3 _ATDDR3.Word#define ATDDR3_BIT6 _ATDDR3.Bits.BIT6#define ATDDR3_BIT7 _ATDDR3.Bits.BIT7#define ATDDR3_BIT8 _ATDDR3.Bits.BIT8#define ATDDR3_BIT9 _ATDDR3.Bits.BIT9#define ATDDR3_BIT10 _ATDDR3.Bits.BIT10#define ATDDR3_BIT11 _ATDDR3.Bits.BIT11#define ATDDR3_BIT12 _ATDDR3.Bits.BIT12#define ATDDR3_BIT13 _ATDDR3.Bits.BIT13#define ATDDR3_BIT14 _ATDDR3.Bits.BIT14#define ATDDR3_BIT15 _ATDDR3.Bits.BIT15#define ATDDR3_BIT_6 _ATDDR3.MergedBits.grpBIT_6#define ATDDR3_BIT ATDDR3_BIT_6/*** ATDDR4 - A/D Conversion Result Register 4; 0x00000098 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR4H - A/D Conversion Result Register 4 High; 0x00000098 ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR4HSTR;#define ATDDR4H _ATDDR4.Overlap_STR.ATDDR4HSTR.Byte#define ATDDR4H_BIT8 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT8#define ATDDR4H_BIT9 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT9#define ATDDR4H_BIT10 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT10#define ATDDR4H_BIT11 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT11#define ATDDR4H_BIT12 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT12#define ATDDR4H_BIT13 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT13#define ATDDR4H_BIT14 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT14#define ATDDR4H_BIT15 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT15#define ATDDR4H_BIT_8 _ATDDR4.Overlap_STR.ATDDR4HSTR.MergedBits.grpBIT_8#define ATDDR4H_BIT ATDDR4H_BIT_8/*** ATDDR4L - A/D Conversion Result Register 4 Low; 0x00000099 ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR4LSTR;#define ATDDR4L _ATDDR4.Overlap_STR.ATDDR4LSTR.Byte#define ATDDR4L_BIT6 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT6#define ATDDR4L_BIT7 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT7#define ATDDR4L_BIT_6 _ATDDR4.Overlap_STR.ATDDR4LSTR.MergedBits.grpBIT_6#define ATDDR4L_BIT ATDDR4L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR4STR;extern volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098);#define ATDDR4 _ATDDR4.Word#define ATDDR4_BIT6 _ATDDR4.Bits.BIT6#define ATDDR4_BIT7 _ATDDR4.Bits.BIT7#define ATDDR4_BIT8 _ATDDR4.Bits.BIT8#define ATDDR4_BIT9 _ATDDR4.Bits.BIT9#define ATDDR4_BIT10 _ATDDR4.Bits.BIT10#define ATDDR4_BIT11 _ATDDR4.Bits.BIT11#define ATDDR4_BIT12 _ATDDR4.Bits.BIT12#define ATDDR4_BIT13 _ATDDR4.Bits.BIT13#define ATDDR4_BIT14 _ATDDR4.Bits.BIT14#define ATDDR4_BIT15 _ATDDR4.Bits.BIT15#define ATDDR4_BIT_6 _ATDDR4.MergedBits.grpBIT_6#define ATDDR4_BIT ATDDR4_BIT_6/*** ATDDR5 - A/D Conversion Result Register 5; 0x0000009A ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR5H - A/D Conversion Result Register 5 High; 0x0000009A ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR5HSTR;#define ATDDR5H _ATDDR5.Overlap_STR.ATDDR5HSTR.Byte#define ATDDR5H_BIT8 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT8#define ATDDR5H_BIT9 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT9#define ATDDR5H_BIT10 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT10#define ATDDR5H_BIT11 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT11#define ATDDR5H_BIT12 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT12#define ATDDR5H_BIT13 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT13#define ATDDR5H_BIT14 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT14#define ATDDR5H_BIT15 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT15#define ATDDR5H_BIT_8 _ATDDR5.Overlap_STR.ATDDR5HSTR.MergedBits.grpBIT_8#define ATDDR5H_BIT ATDDR5H_BIT_8/*** ATDDR5L - A/D Conversion Result Register 5 Low; 0x0000009B ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR5LSTR;#define ATDDR5L _ATDDR5.Overlap_STR.ATDDR5LSTR.Byte#define ATDDR5L_BIT6 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT6#define ATDDR5L_BIT7 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT7#define ATDDR5L_BIT_6 _ATDDR5.Overlap_STR.ATDDR5LSTR.MergedBits.grpBIT_6#define ATDDR5L_BIT ATDDR5L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR5STR;extern volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A);#define ATDDR5 _ATDDR5.Word#define ATDDR5_BIT6 _ATDDR5.Bits.BIT6#define ATDDR5_BIT7 _ATDDR5.Bits.BIT7#define ATDDR5_BIT8 _ATDDR5.Bits.BIT8#define ATDDR5_BIT9 _ATDDR5.Bits.BIT9#define ATDDR5_BIT10 _ATDDR5.Bits.BIT10#define ATDDR5_BIT11 _ATDDR5.Bits.BIT11#define ATDDR5_BIT12 _ATDDR5.Bits.BIT12#define ATDDR5_BIT13 _ATDDR5.Bits.BIT13#define ATDDR5_BIT14 _ATDDR5.Bits.BIT14#define ATDDR5_BIT15 _ATDDR5.Bits.BIT15#define ATDDR5_BIT_6 _ATDDR5.MergedBits.grpBIT_6#define ATDDR5_BIT ATDDR5_BIT_6/*** ATDDR6 - A/D Conversion Result Register 6; 0x0000009C ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR6H - A/D Conversion Result Register 6 High; 0x0000009C ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR6HSTR;#define ATDDR6H _ATDDR6.Overlap_STR.ATDDR6HSTR.Byte#define ATDDR6H_BIT8 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT8#define ATDDR6H_BIT9 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT9#define ATDDR6H_BIT10 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT10#define ATDDR6H_BIT11 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT11#define ATDDR6H_BIT12 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT12#define ATDDR6H_BIT13 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT13#define ATDDR6H_BIT14 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT14#define ATDDR6H_BIT15 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT15#define ATDDR6H_BIT_8 _ATDDR6.Overlap_STR.ATDDR6HSTR.MergedBits.grpBIT_8#define ATDDR6H_BIT ATDDR6H_BIT_8/*** ATDDR6L - A/D Conversion Result Register 6 Low; 0x0000009D ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR6LSTR;#define ATDDR6L _ATDDR6.Overlap_STR.ATDDR6LSTR.Byte#define ATDDR6L_BIT6 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT6#define ATDDR6L_BIT7 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT7#define ATDDR6L_BIT_6 _ATDDR6.Overlap_STR.ATDDR6LSTR.MergedBits.grpBIT_6#define ATDDR6L_BIT ATDDR6L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR6STR;extern volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C);#define ATDDR6 _ATDDR6.Word#define ATDDR6_BIT6 _ATDDR6.Bits.BIT6#define ATDDR6_BIT7 _ATDDR6.Bits.BIT7#define ATDDR6_BIT8 _ATDDR6.Bits.BIT8#define ATDDR6_BIT9 _ATDDR6.Bits.BIT9#define ATDDR6_BIT10 _ATDDR6.Bits.BIT10#define ATDDR6_BIT11 _ATDDR6.Bits.BIT11#define ATDDR6_BIT12 _ATDDR6.Bits.BIT12#define ATDDR6_BIT13 _ATDDR6.Bits.BIT13#define ATDDR6_BIT14 _ATDDR6.Bits.BIT14#define ATDDR6_BIT15 _ATDDR6.Bits.BIT15#define ATDDR6_BIT_6 _ATDDR6.MergedBits.grpBIT_6#define ATDDR6_BIT ATDDR6_BIT_6/*** ATDDR7 - A/D Conversion Result Register 7; 0x0000009E ***/typedef union {word Word;/* Overlapped registers: */struct {/*** ATDDR7H - A/D Conversion Result Register 7 High; 0x0000009E ***/union {byte Byte;struct {byte BIT8 :1; /* Bit 8 */byte BIT9 :1; /* Bit 9 */byte BIT10 :1; /* Bit 10 */byte BIT11 :1; /* Bit 11 */byte BIT12 :1; /* Bit 12 */byte BIT13 :1; /* Bit 13 */byte BIT14 :1; /* Bit 14 */byte BIT15 :1; /* Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} ATDDR7HSTR;#define ATDDR7H _ATDDR7.Overlap_STR.ATDDR7HSTR.Byte#define ATDDR7H_BIT8 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT8#define ATDDR7H_BIT9 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT9#define ATDDR7H_BIT10 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT10#define ATDDR7H_BIT11 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT11#define ATDDR7H_BIT12 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT12#define ATDDR7H_BIT13 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT13#define ATDDR7H_BIT14 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT14#define ATDDR7H_BIT15 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT15#define ATDDR7H_BIT_8 _ATDDR7.Overlap_STR.ATDDR7HSTR.MergedBits.grpBIT_8#define ATDDR7H_BIT ATDDR7H_BIT_8/*** ATDDR7L - A/D Conversion Result Register 7 Low; 0x0000009F ***/union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte BIT6 :1; /* Bit 6 */byte BIT7 :1; /* Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpBIT_6 :2;} MergedBits;} ATDDR7LSTR;#define ATDDR7L _ATDDR7.Overlap_STR.ATDDR7LSTR.Byte#define ATDDR7L_BIT6 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT6#define ATDDR7L_BIT7 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT7#define ATDDR7L_BIT_6 _ATDDR7.Overlap_STR.ATDDR7LSTR.MergedBits.grpBIT_6#define ATDDR7L_BIT ATDDR7L_BIT_6} Overlap_STR;struct {word :1;word :1;word :1;word :1;word :1;word :1;word BIT6 :1; /* Bit 6 */word BIT7 :1; /* Bit 7 */word BIT8 :1; /* Bit 8 */word BIT9 :1; /* Bit 9 */word BIT10 :1; /* Bit 10 */word BIT11 :1; /* Bit 11 */word BIT12 :1; /* Bit 12 */word BIT13 :1; /* Bit 13 */word BIT14 :1; /* Bit 14 */word BIT15 :1; /* Bit 15 */} Bits;struct {word :1;word :1;word :1;word :1;word :1;word :1;word grpBIT_6 :10;} MergedBits;} ATDDR7STR;extern volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E);#define ATDDR7 _ATDDR7.Word#define ATDDR7_BIT6 _ATDDR7.Bits.BIT6#define ATDDR7_BIT7 _ATDDR7.Bits.BIT7#define ATDDR7_BIT8 _ATDDR7.Bits.BIT8#define ATDDR7_BIT9 _ATDDR7.Bits.BIT9#define ATDDR7_BIT10 _ATDDR7.Bits.BIT10#define ATDDR7_BIT11 _ATDDR7.Bits.BIT11#define ATDDR7_BIT12 _ATDDR7.Bits.BIT12#define ATDDR7_BIT13 _ATDDR7.Bits.BIT13#define ATDDR7_BIT14 _ATDDR7.Bits.BIT14#define ATDDR7_BIT15 _ATDDR7.Bits.BIT15#define ATDDR7_BIT_6 _ATDDR7.MergedBits.grpBIT_6#define ATDDR7_BIT ATDDR7_BIT_6/*** SCIBD - SCI Baud Rate Register; 0x000000C8 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** SCIBDH - SCI Baud Rate Register High; 0x000000C8 ***/union {byte Byte;struct {byte SBR8 :1; /* SCI baud rate Bit 8 */byte SBR9 :1; /* SCI baud rate Bit 9 */byte SBR10 :1; /* SCI baud rate Bit 10 */byte SBR11 :1; /* SCI baud rate Bit 11 */byte SBR12 :1; /* SCI baud rate Bit 12 */byte :1;byte :1;byte :1;} Bits;struct {byte grpSBR_8 :5;byte :1;byte :1;byte :1;} MergedBits;} SCIBDHSTR;#define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte#define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8#define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9#define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10#define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11#define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12#define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8#define SCIBDH_SBR SCIBDH_SBR_8/*** SCIBDL - SCI Baud Rate Register Low; 0x000000C9 ***/union {byte Byte;struct {byte SBR0 :1; /* SCI baud rate Bit 0 */byte SBR1 :1; /* SCI baud rate Bit 1 */byte SBR2 :1; /* SCI baud rate Bit 2 */byte SBR3 :1; /* SCI baud rate Bit 3 */byte SBR4 :1; /* SCI baud rate Bit 4 */byte SBR5 :1; /* SCI baud rate Bit 5 */byte SBR6 :1; /* SCI baud rate Bit 6 */byte SBR7 :1; /* SCI baud rate Bit 7 */} Bits;struct {byte grpSBR :8;} MergedBits;} SCIBDLSTR;#define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte#define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0#define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1#define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2#define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3#define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4#define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5#define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6#define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7#define SCIBDL_SBR _SCIBD.Overlap_STR.SCIBDLSTR.MergedBits.grpSBR} Overlap_STR;struct {word SBR0 :1; /* SCI baud rate Bit 0 */word SBR1 :1; /* SCI baud rate Bit 1 */word SBR2 :1; /* SCI baud rate Bit 2 */word SBR3 :1; /* SCI baud rate Bit 3 */word SBR4 :1; /* SCI baud rate Bit 4 */word SBR5 :1; /* SCI baud rate Bit 5 */word SBR6 :1; /* SCI baud rate Bit 6 */word SBR7 :1; /* SCI baud rate Bit 7 */word SBR8 :1; /* SCI baud rate Bit 8 */word SBR9 :1; /* SCI baud rate Bit 9 */word SBR10 :1; /* SCI baud rate Bit 10 */word SBR11 :1; /* SCI baud rate Bit 11 */word SBR12 :1; /* SCI baud rate Bit 12 */word :1;word :1;word :1;} Bits;struct {word grpSBR :13;word :1;word :1;word :1;} MergedBits;} SCIBDSTR;extern volatile SCIBDSTR _SCIBD @(REG_BASE + 0x000000C8);#define SCIBD _SCIBD.Word#define SCIBD_SBR0 _SCIBD.Bits.SBR0#define SCIBD_SBR1 _SCIBD.Bits.SBR1#define SCIBD_SBR2 _SCIBD.Bits.SBR2#define SCIBD_SBR3 _SCIBD.Bits.SBR3#define SCIBD_SBR4 _SCIBD.Bits.SBR4#define SCIBD_SBR5 _SCIBD.Bits.SBR5#define SCIBD_SBR6 _SCIBD.Bits.SBR6#define SCIBD_SBR7 _SCIBD.Bits.SBR7#define SCIBD_SBR8 _SCIBD.Bits.SBR8#define SCIBD_SBR9 _SCIBD.Bits.SBR9#define SCIBD_SBR10 _SCIBD.Bits.SBR10#define SCIBD_SBR11 _SCIBD.Bits.SBR11#define SCIBD_SBR12 _SCIBD.Bits.SBR12#define SCIBD_SBR _SCIBD.MergedBits.grpSBR/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000EC ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000EC ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMCNT0STR;#define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte#define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT/*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000ED ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMCNT1STR;#define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte#define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMCNT01STR;extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC);#define PWMCNT01 _PWMCNT01.Word#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000EE ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000EE ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMCNT2STR;#define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte#define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT/*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000EF ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMCNT3STR;#define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte#define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMCNT23STR;extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE);#define PWMCNT23 _PWMCNT23.Word#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000F0 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000F0 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMCNT4STR;#define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte#define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT/*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000F1 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMCNT5STR;#define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte#define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMCNT45STR;extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0);#define PWMCNT45 _PWMCNT45.Word#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000F2 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMPER0 - PWM Channel Period 0 Register; 0x000000F2 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMPER0STR;#define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte#define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT/*** PWMPER1 - PWM Channel Period 1 Register; 0x000000F3 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMPER1STR;#define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte#define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMPER01STR;extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2);#define PWMPER01 _PWMPER01.Word#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000F4 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMPER2 - PWM Channel Period 2 Register; 0x000000F4 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMPER2STR;#define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte#define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT/*** PWMPER3 - PWM Channel Period 3 Register; 0x000000F5 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMPER3STR;#define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte#define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMPER23STR;extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4);#define PWMPER23 _PWMPER23.Word#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000F6 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMPER4 - PWM Channel Period 4 Register; 0x000000F6 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMPER4STR;#define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte#define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT/*** PWMPER5 - PWM Channel Period 5 Register; 0x000000F7 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMPER5STR;#define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte#define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMPER45STR;extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6);#define PWMPER45 _PWMPER45.Word#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000F8 ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000F8 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMDTY0STR;#define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte#define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT/*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000F9 ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMDTY1STR;#define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte#define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMDTY01STR;extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8);#define PWMDTY01 _PWMDTY01.Word#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000FA ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000FA ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMDTY2STR;#define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte#define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT/*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000FB ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMDTY3STR;#define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte#define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMDTY23STR;extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA);#define PWMDTY23 _PWMDTY23.Word#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000FC ***/typedef union {word Word;/* Overlapped registers: */struct {/*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000FC ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMDTY4STR;#define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte#define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT/*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000FD ***/union {byte Byte;struct {byte grpBIT :8;} MergedBits;} PWMDTY5STR;#define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte#define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT} Overlap_STR;struct {word grpBIT :16;} MergedBits;} PWMDTY45STR;extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC);#define PWMDTY45 _PWMDTY45.Word#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT/*** PORTE - Port E Register; 0x00000008 ***/typedef union {byte Byte;struct {byte BIT0 :1; /* Port E Bit 0 */byte BIT1 :1; /* Port E Bit 1 */byte BIT2 :1; /* Port E Bit 2 */byte BIT3 :1; /* Port E Bit 3 */byte BIT4 :1; /* Port E Bit 4 */byte BIT5 :1; /* Port E Bit 5 */byte BIT6 :1; /* Port E Bit 6 */byte BIT7 :1; /* Port E Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} PORTESTR;extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);#define PORTE _PORTE.Byte#define PORTE_BIT0 _PORTE.Bits.BIT0#define PORTE_BIT1 _PORTE.Bits.BIT1#define PORTE_BIT2 _PORTE.Bits.BIT2#define PORTE_BIT3 _PORTE.Bits.BIT3#define PORTE_BIT4 _PORTE.Bits.BIT4#define PORTE_BIT5 _PORTE.Bits.BIT5#define PORTE_BIT6 _PORTE.Bits.BIT6#define PORTE_BIT7 _PORTE.Bits.BIT7#define PORTE_BIT _PORTE.MergedBits.grpBIT/*** DDRE - Port E Data Direction Register; 0x00000009 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte BIT2 :1; /* Data Direction Port A Bit 2 */byte BIT3 :1; /* Data Direction Port A Bit 3 */byte BIT4 :1; /* Data Direction Port A Bit 4 */byte BIT5 :1; /* Data Direction Port A Bit 5 */byte BIT6 :1; /* Data Direction Port A Bit 6 */byte BIT7 :1; /* Data Direction Port A Bit 7 */} Bits;struct {byte :1;byte :1;byte grpBIT_2 :6;} MergedBits;} DDRESTR;extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);#define DDRE _DDRE.Byte#define DDRE_BIT2 _DDRE.Bits.BIT2#define DDRE_BIT3 _DDRE.Bits.BIT3#define DDRE_BIT4 _DDRE.Bits.BIT4#define DDRE_BIT5 _DDRE.Bits.BIT5#define DDRE_BIT6 _DDRE.Bits.BIT6#define DDRE_BIT7 _DDRE.Bits.BIT7#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2#define DDRE_BIT DDRE_BIT_2/*** PEAR - Port E Assignment Register; 0x0000000A ***/typedef union {byte Byte;struct {byte :1;byte :1;byte RDWE :1; /* Read / Write Enable */byte LSTRE :1; /* Low Strobe (LSTRB) Enable */byte NECLK :1; /* No External E Clock */byte PIPOE :1; /* Pipe Status Signal Output Enable */byte :1;byte NOACCE :1; /* CPU No Access Output Enable */} Bits;} PEARSTR;extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);#define PEAR _PEAR.Byte#define PEAR_RDWE _PEAR.Bits.RDWE#define PEAR_LSTRE _PEAR.Bits.LSTRE#define PEAR_NECLK _PEAR.Bits.NECLK#define PEAR_PIPOE _PEAR.Bits.PIPOE#define PEAR_NOACCE _PEAR.Bits.NOACCE/*** MODE - Mode Register; 0x0000000B ***/typedef union {byte Byte;struct {byte EME :1; /* Emulate Port E */byte EMK :1; /* Emulate Port K */byte :1;byte IVIS :1; /* Internal Visibility */byte :1;byte MODA :1; /* Mode Select Bit A */byte MODB :1; /* Mode Select Bit B */byte MODC :1; /* Mode Select Bit C */} Bits;} MODESTR;extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);#define MODE _MODE.Byte#define MODE_EME _MODE.Bits.EME#define MODE_EMK _MODE.Bits.EMK#define MODE_IVIS _MODE.Bits.IVIS#define MODE_MODA _MODE.Bits.MODA#define MODE_MODB _MODE.Bits.MODB#define MODE_MODC _MODE.Bits.MODC/*** PUCR - Pull-Up Control Register; 0x0000000C ***/typedef union {byte Byte;struct {byte PUPAE :1; /* Pull-Up Port A Enable */byte PUPBE :1; /* Pull-Up Port B Enable */byte :1;byte :1;byte PUPEE :1; /* Pull-Up Port E Enable */byte :1;byte :1;byte PUPKE :1; /* Pull-Up Port K Enable */} Bits;} PUCRSTR;extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);#define PUCR _PUCR.Byte#define PUCR_PUPAE _PUCR.Bits.PUPAE#define PUCR_PUPBE _PUCR.Bits.PUPBE#define PUCR_PUPEE _PUCR.Bits.PUPEE#define PUCR_PUPKE _PUCR.Bits.PUPKE/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/typedef union {byte Byte;struct {byte RDPA :1; /* Reduced Drive of Port A */byte RDPB :1; /* Reduced Drive of Port B */byte :1;byte :1;byte RDPE :1; /* Reduced Drive of Port E */byte :1;byte :1;byte RDPK :1; /* Reduced Drive of Port K */} Bits;} RDRIVSTR;extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);#define RDRIV _RDRIV.Byte#define RDRIV_RDPA _RDRIV.Bits.RDPA#define RDRIV_RDPB _RDRIV.Bits.RDPB#define RDRIV_RDPE _RDRIV.Bits.RDPE#define RDRIV_RDPK _RDRIV.Bits.RDPK/*** EBICTL - External Bus Interface Control; 0x0000000E ***/typedef union {byte Byte;struct {byte ESTR :1; /* E Stretches */byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;} EBICTLSTR;extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);#define EBICTL _EBICTL.Byte#define EBICTL_ESTR _EBICTL.Bits.ESTR/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/typedef union {byte Byte;struct {byte RAMHAL :1; /* Internal RAM map alignment */byte :1;byte :1;byte RAM11 :1; /* Internal RAM map position Bit 11 */byte RAM12 :1; /* Internal RAM map position Bit 12 */byte RAM13 :1; /* Internal RAM map position Bit 13 */byte RAM14 :1; /* Internal RAM map position Bit 14 */byte RAM15 :1; /* Internal RAM map position Bit 15 */} Bits;struct {byte :1;byte :1;byte :1;byte grpRAM_11 :5;} MergedBits;} INITRMSTR;extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);#define INITRM _INITRM.Byte#define INITRM_RAMHAL _INITRM.Bits.RAMHAL#define INITRM_RAM11 _INITRM.Bits.RAM11#define INITRM_RAM12 _INITRM.Bits.RAM12#define INITRM_RAM13 _INITRM.Bits.RAM13#define INITRM_RAM14 _INITRM.Bits.RAM14#define INITRM_RAM15 _INITRM.Bits.RAM15#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11#define INITRM_RAM INITRM_RAM_11/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte REG11 :1; /* Internal register map position REG11 */byte REG12 :1; /* Internal register map position REG12 */byte REG13 :1; /* Internal register map position REG13 */byte REG14 :1; /* Internal register map position REG14 */byte :1;} Bits;struct {byte :1;byte :1;byte :1;byte grpREG_11 :4;byte :1;} MergedBits;} INITRGSTR;extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);#define INITRG _INITRG.Byte#define INITRG_REG11 _INITRG.Bits.REG11#define INITRG_REG12 _INITRG.Bits.REG12#define INITRG_REG13 _INITRG.Bits.REG13#define INITRG_REG14 _INITRG.Bits.REG14#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11#define INITRG_REG INITRG_REG_11/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/typedef union {byte Byte;struct {byte EEON :1; /* Internal EEPROM On */byte :1;byte :1;byte :1;byte EE12 :1; /* Internal EEPROM map position Bit 12 */byte EE13 :1; /* Internal EEPROM map position Bit 13 */byte EE14 :1; /* Internal EEPROM map position Bit 14 */byte EE15 :1; /* Internal EEPROM map position Bit 15 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte grpEE_12 :4;} MergedBits;} INITEESTR;extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);#define INITEE _INITEE.Byte#define INITEE_EEON _INITEE.Bits.EEON#define INITEE_EE12 _INITEE.Bits.EE12#define INITEE_EE13 _INITEE.Bits.EE13#define INITEE_EE14 _INITEE.Bits.EE14#define INITEE_EE15 _INITEE.Bits.EE15#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12#define INITEE_EE INITEE_EE_12/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/typedef union {byte Byte;struct {byte ROMON :1; /* Enable Flash EEPROM */byte ROMHM :1; /* Flash EEPROM only in second half of memory map */byte EXSTR0 :1; /* External Access Stretch Bit 0 */byte EXSTR1 :1; /* External Access Stretch Bit 1 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte :1;byte :1;byte grpEXSTR :2;byte :1;byte :1;byte :1;byte :1;} MergedBits;} MISCSTR;extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);#define MISC _MISC.Byte#define MISC_ROMON _MISC.Bits.ROMON#define MISC_ROMHM _MISC.Bits.ROMHM#define MISC_EXSTR0 _MISC.Bits.EXSTR0#define MISC_EXSTR1 _MISC.Bits.EXSTR1#define MISC_EXSTR _MISC.MergedBits.grpEXSTR/*** MTST0 - MTST0; 0x00000014 ***/typedef union {byte Byte;struct {byte BIT0 :1; /* MTST0 Bit 0 */byte BIT1 :1; /* MTST0 Bit 1 */byte BIT2 :1; /* MTST0 Bit 2 */byte BIT3 :1; /* MTST0 Bit 3 */byte BIT4 :1; /* MTST0 Bit 4 */byte BIT5 :1; /* MTST0 Bit 5 */byte BIT6 :1; /* MTST0 Bit 6 */byte BIT7 :1; /* MTST0 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} MTST0STR;extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);#define MTST0 _MTST0.Byte#define MTST0_BIT0 _MTST0.Bits.BIT0#define MTST0_BIT1 _MTST0.Bits.BIT1#define MTST0_BIT2 _MTST0.Bits.BIT2#define MTST0_BIT3 _MTST0.Bits.BIT3#define MTST0_BIT4 _MTST0.Bits.BIT4#define MTST0_BIT5 _MTST0.Bits.BIT5#define MTST0_BIT6 _MTST0.Bits.BIT6#define MTST0_BIT7 _MTST0.Bits.BIT7#define MTST0_BIT _MTST0.MergedBits.grpBIT/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/typedef union {byte Byte;struct {byte ADR0 :1; /* Test register select Bit 0 */byte ADR1 :1; /* Test register select Bit 1 */byte ADR2 :1; /* Test register select Bit 2 */byte ADR3 :1; /* Test register select Bit 3 */byte WRTINT :1; /* Write to the Interrupt Test Registers */byte :1;byte :1;byte :1;} Bits;struct {byte grpADR :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} ITCRSTR;extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);#define ITCR _ITCR.Byte#define ITCR_ADR0 _ITCR.Bits.ADR0#define ITCR_ADR1 _ITCR.Bits.ADR1#define ITCR_ADR2 _ITCR.Bits.ADR2#define ITCR_ADR3 _ITCR.Bits.ADR3#define ITCR_WRTINT _ITCR.Bits.WRTINT#define ITCR_ADR _ITCR.MergedBits.grpADR/*** ITEST - Interrupt Test Register; 0x00000016 ***/typedef union {byte Byte;struct {byte INT0 :1; /* Interrupt Test Register Bit 0 */byte INT2 :1; /* Interrupt Test Register Bit 1 */byte INT4 :1; /* Interrupt Test Register Bit 2 */byte INT6 :1; /* Interrupt Test Register Bit 3 */byte INT8 :1; /* Interrupt Test Register Bit 4 */byte INTA :1; /* Interrupt Test Register Bit 5 */byte INTC :1; /* Interrupt Test Register Bit 6 */byte INTE :1; /* Interrupt Test Register Bit 7 */} Bits;} ITESTSTR;extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);#define ITEST _ITEST.Byte#define ITEST_INT0 _ITEST.Bits.INT0#define ITEST_INT2 _ITEST.Bits.INT2#define ITEST_INT4 _ITEST.Bits.INT4#define ITEST_INT6 _ITEST.Bits.INT6#define ITEST_INT8 _ITEST.Bits.INT8#define ITEST_INTA _ITEST.Bits.INTA#define ITEST_INTC _ITEST.Bits.INTC#define ITEST_INTE _ITEST.Bits.INTE/*** MTST1 - MTST1; 0x00000017 ***/typedef union {byte Byte;struct {byte BIT0 :1; /* MTST1 Bit 0 */byte BIT1 :1; /* MTST1 Bit 1 */byte BIT2 :1; /* MTST1 Bit 2 */byte BIT3 :1; /* MTST1 Bit 3 */byte BIT4 :1; /* MTST1 Bit 4 */byte BIT5 :1; /* MTST1 Bit 5 */byte BIT6 :1; /* MTST1 Bit 6 */byte BIT7 :1; /* MTST1 Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} MTST1STR;extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);#define MTST1 _MTST1.Byte#define MTST1_BIT0 _MTST1.Bits.BIT0#define MTST1_BIT1 _MTST1.Bits.BIT1#define MTST1_BIT2 _MTST1.Bits.BIT2#define MTST1_BIT3 _MTST1.Bits.BIT3#define MTST1_BIT4 _MTST1.Bits.BIT4#define MTST1_BIT5 _MTST1.Bits.BIT5#define MTST1_BIT6 _MTST1.Bits.BIT6#define MTST1_BIT7 _MTST1.Bits.BIT7#define MTST1_BIT _MTST1.MergedBits.grpBIT/*** PARTIDH - Part ID Register High; 0x0000001A ***/typedef union {byte Byte;struct {byte ID15 :1; /* Part ID Register Bit 15 */byte ID14 :1; /* Part ID Register Bit 14 */byte ID13 :1; /* Part ID Register Bit 13 */byte ID12 :1; /* Part ID Register Bit 12 */byte ID11 :1; /* Part ID Register Bit 11 */byte ID10 :1; /* Part ID Register Bit 10 */byte ID9 :1; /* Part ID Register Bit 9 */byte ID8 :1; /* Part ID Register Bit 8 */} Bits;} PARTIDHSTR;extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);#define PARTIDH _PARTIDH.Byte#define PARTIDH_ID15 _PARTIDH.Bits.ID15#define PARTIDH_ID14 _PARTIDH.Bits.ID14#define PARTIDH_ID13 _PARTIDH.Bits.ID13#define PARTIDH_ID12 _PARTIDH.Bits.ID12#define PARTIDH_ID11 _PARTIDH.Bits.ID11#define PARTIDH_ID10 _PARTIDH.Bits.ID10#define PARTIDH_ID9 _PARTIDH.Bits.ID9#define PARTIDH_ID8 _PARTIDH.Bits.ID8/*** PARTIDL - Part ID Register Low; 0x0000001B ***/typedef union {byte Byte;struct {byte ID0 :1; /* Part ID Register Bit 0 */byte ID1 :1; /* Part ID Register Bit 1 */byte ID2 :1; /* Part ID Register Bit 2 */byte ID3 :1; /* Part ID Register Bit 3 */byte ID4 :1; /* Part ID Register Bit 4 */byte ID5 :1; /* Part ID Register Bit 5 */byte ID6 :1; /* Part ID Register Bit 6 */byte ID7 :1; /* Part ID Register Bit 7 */} Bits;struct {byte grpID :8;} MergedBits;} PARTIDLSTR;extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);#define PARTIDL _PARTIDL.Byte#define PARTIDL_ID0 _PARTIDL.Bits.ID0#define PARTIDL_ID1 _PARTIDL.Bits.ID1#define PARTIDL_ID2 _PARTIDL.Bits.ID2#define PARTIDL_ID3 _PARTIDL.Bits.ID3#define PARTIDL_ID4 _PARTIDL.Bits.ID4#define PARTIDL_ID5 _PARTIDL.Bits.ID5#define PARTIDL_ID6 _PARTIDL.Bits.ID6#define PARTIDL_ID7 _PARTIDL.Bits.ID7#define PARTIDL_ID _PARTIDL.MergedBits.grpID/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/typedef union {byte Byte;struct {byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */byte :1;byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */byte :1;byte reg_sw0 :1; /* Allocated System Register Space */} Bits;struct {byte grpram_sw :3;byte :1;byte grpeep_sw :2;byte :1;byte grpreg_sw :1;} MergedBits;} MEMSIZ0STR;extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);#define MEMSIZ0 _MEMSIZ0.Byte#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/typedef union {byte Byte;struct {byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */byte :1;byte :1;byte :1;byte :1;byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */} Bits;struct {byte grppag_sw :2;byte :1;byte :1;byte :1;byte :1;byte grprom_sw :2;} MergedBits;} MEMSIZ1STR;extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);#define MEMSIZ1 _MEMSIZ1.Byte#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw/*** INTCR - Interrupt Control Register; 0x0000001E ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte IRQEN :1; /* External IRQ Enable */byte IRQE :1; /* IRQ Select Edge Sensitive Only */} Bits;} INTCRSTR;extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);#define INTCR _INTCR.Byte#define INTCR_IRQEN _INTCR.Bits.IRQEN#define INTCR_IRQE _INTCR.Bits.IRQE/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/typedef union {byte Byte;struct {byte :1;byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */} Bits;struct {byte :1;byte grpPSEL_1 :7;} MergedBits;} HPRIOSTR;extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);#define HPRIO _HPRIO.Byte#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1#define HPRIO_PSEL HPRIO_PSEL_1/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte BKTAG :1; /* Breakpoint on Tag */byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */byte BKFULL :1; /* Full Breakpoint Mode Enable */byte BKEN :1; /* Breakpoint Enable */} Bits;} BKPCT0STR;extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);#define BKPCT0 _BKPCT0.Byte#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL#define BKPCT0_BKEN _BKPCT0.Bits.BKEN/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/typedef union {byte Byte;struct {byte BK1RW :1; /* R/W Compare Value 1 */byte BK1RWE :1; /* R/W Compare Enable 1 */byte BK0RW :1; /* R/W Compare Value 0 */byte BK0RWE :1; /* R/W Compare Enable 0 */byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */} Bits;} BKPCT1STR;extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);#define BKPCT1 _BKPCT1.Byte#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/typedef union {byte Byte;struct {byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */byte :1;byte :1;} Bits;struct {byte grpBK0V :6;byte :1;byte :1;} MergedBits;} BKP0XSTR;extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);#define BKP0X _BKP0X.Byte#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/typedef union {byte Byte;struct {byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} BKP0HSTR;extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);#define BKP0H _BKP0H.Byte#define BKP0H_BIT8 _BKP0H.Bits.BIT8#define BKP0H_BIT9 _BKP0H.Bits.BIT9#define BKP0H_BIT10 _BKP0H.Bits.BIT10#define BKP0H_BIT11 _BKP0H.Bits.BIT11#define BKP0H_BIT12 _BKP0H.Bits.BIT12#define BKP0H_BIT13 _BKP0H.Bits.BIT13#define BKP0H_BIT14 _BKP0H.Bits.BIT14#define BKP0H_BIT15 _BKP0H.Bits.BIT15#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8#define BKP0H_BIT BKP0H_BIT_8/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/typedef union {byte Byte;struct {byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} BKP0LSTR;extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);#define BKP0L _BKP0L.Byte#define BKP0L_BIT0 _BKP0L.Bits.BIT0#define BKP0L_BIT1 _BKP0L.Bits.BIT1#define BKP0L_BIT2 _BKP0L.Bits.BIT2#define BKP0L_BIT3 _BKP0L.Bits.BIT3#define BKP0L_BIT4 _BKP0L.Bits.BIT4#define BKP0L_BIT5 _BKP0L.Bits.BIT5#define BKP0L_BIT6 _BKP0L.Bits.BIT6#define BKP0L_BIT7 _BKP0L.Bits.BIT7#define BKP0L_BIT _BKP0L.MergedBits.grpBIT/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/typedef union {byte Byte;struct {byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */byte :1;byte :1;} Bits;struct {byte grpBK1V :6;byte :1;byte :1;} MergedBits;} BKP1XSTR;extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);#define BKP1X _BKP1X.Byte#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/typedef union {byte Byte;struct {byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */} Bits;struct {byte grpBIT_8 :8;} MergedBits;} BKP1HSTR;extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);#define BKP1H _BKP1H.Byte#define BKP1H_BIT8 _BKP1H.Bits.BIT8#define BKP1H_BIT9 _BKP1H.Bits.BIT9#define BKP1H_BIT10 _BKP1H.Bits.BIT10#define BKP1H_BIT11 _BKP1H.Bits.BIT11#define BKP1H_BIT12 _BKP1H.Bits.BIT12#define BKP1H_BIT13 _BKP1H.Bits.BIT13#define BKP1H_BIT14 _BKP1H.Bits.BIT14#define BKP1H_BIT15 _BKP1H.Bits.BIT15#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8#define BKP1H_BIT BKP1H_BIT_8/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/typedef union {byte Byte;struct {byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} BKP1LSTR;extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);#define BKP1L _BKP1L.Byte#define BKP1L_BIT0 _BKP1L.Bits.BIT0#define BKP1L_BIT1 _BKP1L.Bits.BIT1#define BKP1L_BIT2 _BKP1L.Bits.BIT2#define BKP1L_BIT3 _BKP1L.Bits.BIT3#define BKP1L_BIT4 _BKP1L.Bits.BIT4#define BKP1L_BIT5 _BKP1L.Bits.BIT5#define BKP1L_BIT6 _BKP1L.Bits.BIT6#define BKP1L_BIT7 _BKP1L.Bits.BIT7#define BKP1L_BIT _BKP1L.MergedBits.grpBIT/*** PPAGE - Page Index Register; 0x00000030 ***/typedef union {byte Byte;struct {byte PIX0 :1; /* Page Index Register Bit 0 */byte PIX1 :1; /* Page Index Register Bit 1 */byte PIX2 :1; /* Page Index Register Bit 2 */byte PIX3 :1; /* Page Index Register Bit 3 */byte PIX4 :1; /* Page Index Register Bit 4 */byte PIX5 :1; /* Page Index Register Bit 5 */byte :1;byte :1;} Bits;struct {byte grpPIX :6;byte :1;byte :1;} MergedBits;} PPAGESTR;extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);#define PPAGE _PPAGE.Byte#define PPAGE_PIX0 _PPAGE.Bits.PIX0#define PPAGE_PIX1 _PPAGE.Bits.PIX1#define PPAGE_PIX2 _PPAGE.Bits.PIX2#define PPAGE_PIX3 _PPAGE.Bits.PIX3#define PPAGE_PIX4 _PPAGE.Bits.PIX4#define PPAGE_PIX5 _PPAGE.Bits.PIX5#define PPAGE_PIX _PPAGE.MergedBits.grpPIX/*** PORTK - Port K Data Register; 0x00000032 ***/typedef union {byte Byte;struct {byte BIT0 :1; /* Port K Bit 0, XAB14 */byte BIT1 :1; /* Port K Bit 1, XAB15 */byte BIT2 :1; /* Port K Bit 2, XAB16 */byte BIT3 :1; /* Port K Bit 3, XAB17 */byte BIT4 :1; /* Port K Bit 4, XAB18 */byte BIT5 :1; /* Port K Bit 5, XAB19 */byte BIT6 :1; /* Port K Bit 6 */byte BIT7 :1; /* Port K Bit 7, ECS/ROMONE */} Bits;struct {byte grpBIT :8;} MergedBits;} PORTKSTR;extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);#define PORTK _PORTK.Byte#define PORTK_BIT0 _PORTK.Bits.BIT0#define PORTK_BIT1 _PORTK.Bits.BIT1#define PORTK_BIT2 _PORTK.Bits.BIT2#define PORTK_BIT3 _PORTK.Bits.BIT3#define PORTK_BIT4 _PORTK.Bits.BIT4#define PORTK_BIT5 _PORTK.Bits.BIT5#define PORTK_BIT6 _PORTK.Bits.BIT6#define PORTK_BIT7 _PORTK.Bits.BIT7#define PORTK_BIT _PORTK.MergedBits.grpBIT/*** DDRK - Port K Data Direction Register; 0x00000033 ***/typedef union {byte Byte;struct {byte DDK0 :1; /* Port K Data Direction Bit 0 */byte DDK1 :1; /* Port K Data Direction Bit 1 */byte DDK2 :1; /* Port K Data Direction Bit 2 */byte DDK3 :1; /* Port K Data Direction Bit 3 */byte DDK4 :1; /* Port K Data Direction Bit 4 */byte DDK5 :1; /* Port K Data Direction Bit 5 */byte :1;byte DDK7 :1; /* Port K Data Direction Bit 7 */} Bits;struct {byte grpDDK :6;byte :1;byte grpDDK_7 :1;} MergedBits;} DDRKSTR;extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);#define DDRK _DDRK.Byte#define DDRK_DDK0 _DDRK.Bits.DDK0#define DDRK_DDK1 _DDRK.Bits.DDK1#define DDRK_DDK2 _DDRK.Bits.DDK2#define DDRK_DDK3 _DDRK.Bits.DDK3#define DDRK_DDK4 _DDRK.Bits.DDK4#define DDRK_DDK5 _DDRK.Bits.DDK5#define DDRK_DDK7 _DDRK.Bits.DDK7#define DDRK_DDK _DDRK.MergedBits.grpDDK/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/typedef union {byte Byte;struct {byte SYN0 :1; /* CRG Synthesizer Bit 0 */byte SYN1 :1; /* CRG Synthesizer Bit 1 */byte SYN2 :1; /* CRG Synthesizer Bit 2 */byte SYN3 :1; /* CRG Synthesizer Bit 3 */byte SYN4 :1; /* CRG Synthesizer Bit 4 */byte SYN5 :1; /* CRG Synthesizer Bit 5 */byte :1;byte :1;} Bits;struct {byte grpSYN :6;byte :1;byte :1;} MergedBits;} SYNRSTR;extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);#define SYNR _SYNR.Byte#define SYNR_SYN0 _SYNR.Bits.SYN0#define SYNR_SYN1 _SYNR.Bits.SYN1#define SYNR_SYN2 _SYNR.Bits.SYN2#define SYNR_SYN3 _SYNR.Bits.SYN3#define SYNR_SYN4 _SYNR.Bits.SYN4#define SYNR_SYN5 _SYNR.Bits.SYN5#define SYNR_SYN _SYNR.MergedBits.grpSYN/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/typedef union {byte Byte;struct {byte REFDV0 :1; /* CRG Reference Divider Bit 0 */byte REFDV1 :1; /* CRG Reference Divider Bit 1 */byte REFDV2 :1; /* CRG Reference Divider Bit 2 */byte REFDV3 :1; /* CRG Reference Divider Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpREFDV :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} REFDVSTR;extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);#define REFDV _REFDV.Byte#define REFDV_REFDV0 _REFDV.Bits.REFDV0#define REFDV_REFDV1 _REFDV.Bits.REFDV1#define REFDV_REFDV2 _REFDV.Bits.REFDV2#define REFDV_REFDV3 _REFDV.Bits.REFDV3#define REFDV_REFDV _REFDV.MergedBits.grpREFDV/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/typedef union {byte Byte;struct {byte TOUT0 :1; /* CRG Test Flags Bit 0 */byte TOUT1 :1; /* CRG Test Flags Bit 1 */byte TOUT2 :1; /* CRG Test Flags Bit 2 */byte TOUT3 :1; /* CRG Test Flags Bit 3 */byte TOUT4 :1; /* CRG Test Flags Bit 4 */byte TOUT5 :1; /* CRG Test Flags Bit 5 */byte TOUT6 :1; /* CRG Test Flags Bit 6 */byte TOUT7 :1; /* CRG Test Flags Bit 7 */} Bits;struct {byte grpTOUT :8;} MergedBits;} CTFLGSTR;extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);#define CTFLG _CTFLG.Byte#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT/*** CRGFLG - CRG Flags Register; 0x00000037 ***/typedef union {byte Byte;struct {byte SCM :1; /* Self-clock mode Status */byte SCMIF :1; /* Self-clock mode Interrupt Flag */byte TRACK :1; /* Track Status */byte LOCK :1; /* Lock Status */byte LOCKIF :1; /* PLL Lock Interrupt Flag */byte :1;byte PORF :1; /* Power on Reset Flag */byte RTIF :1; /* Real Time Interrupt Flag */} Bits;} CRGFLGSTR;extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);#define CRGFLG _CRGFLG.Byte#define CRGFLG_SCM _CRGFLG.Bits.SCM#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF#define CRGFLG_TRACK _CRGFLG.Bits.TRACK#define CRGFLG_LOCK _CRGFLG.Bits.LOCK#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF#define CRGFLG_PORF _CRGFLG.Bits.PORF#define CRGFLG_RTIF _CRGFLG.Bits.RTIF/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/typedef union {byte Byte;struct {byte :1;byte SCMIE :1; /* Self-clock mode Interrupt Enable */byte :1;byte :1;byte LOCKIE :1; /* Lock Interrupt Enable */byte :1;byte :1;byte RTIE :1; /* Real Time Interrupt Enable */} Bits;} CRGINTSTR;extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);#define CRGINT _CRGINT.Byte#define CRGINT_SCMIE _CRGINT.Bits.SCMIE#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE#define CRGINT_RTIE _CRGINT.Bits.RTIE/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/typedef union {byte Byte;struct {byte COPWAI :1; /* COP stops in WAIT mode */byte RTIWAI :1; /* RTI stops in WAIT mode */byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */byte PLLWAI :1; /* PLL stops in WAIT mode */byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */byte SYSWAI :1; /* System clocks stop in WAIT mode */byte PSTP :1; /* Pseudo Stop */byte PLLSEL :1; /* PLL selected for system clock */} Bits;} CLKSELSTR;extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);#define CLKSEL _CLKSEL.Byte#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI#define CLKSEL_CWAI _CLKSEL.Bits.CWAI#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI#define CLKSEL_PSTP _CLKSEL.Bits.PSTP#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/typedef union {byte Byte;struct {byte SCME :1; /* Self-clock mode enable */byte :1;byte :1;byte :1;byte ACQ :1; /* Acquisition */byte AUTO :1; /* Automatic Bandwidth Control */byte PLLON :1; /* Phase Lock Loop On */byte CME :1; /* Crystal Monitor Enable */} Bits;} PLLCTLSTR;extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);#define PLLCTL _PLLCTL.Byte#define PLLCTL_SCME _PLLCTL.Bits.SCME#define PLLCTL_ACQ _PLLCTL.Bits.ACQ#define PLLCTL_AUTO _PLLCTL.Bits.AUTO#define PLLCTL_PLLON _PLLCTL.Bits.PLLON#define PLLCTL_CME _PLLCTL.Bits.CME/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/typedef union {byte Byte;struct {byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */byte :1;} Bits;struct {byte grpRTR :7;byte :1;} MergedBits;} RTICTLSTR;extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);#define RTICTL _RTICTL.Byte#define RTICTL_RTR0 _RTICTL.Bits.RTR0#define RTICTL_RTR1 _RTICTL.Bits.RTR1#define RTICTL_RTR2 _RTICTL.Bits.RTR2#define RTICTL_RTR3 _RTICTL.Bits.RTR3#define RTICTL_RTR4 _RTICTL.Bits.RTR4#define RTICTL_RTR5 _RTICTL.Bits.RTR5#define RTICTL_RTR6 _RTICTL.Bits.RTR6#define RTICTL_RTR _RTICTL.MergedBits.grpRTR/*** COPCTL - CRG COP Control Register; 0x0000003C ***/typedef union {byte Byte;struct {byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */byte :1;byte :1;byte :1;byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */byte WCOP :1; /* Window COP mode */} Bits;struct {byte grpCR :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} COPCTLSTR;extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);#define COPCTL _COPCTL.Byte#define COPCTL_CR0 _COPCTL.Bits.CR0#define COPCTL_CR1 _COPCTL.Bits.CR1#define COPCTL_CR2 _COPCTL.Bits.CR2#define COPCTL_RSBCK _COPCTL.Bits.RSBCK#define COPCTL_WCOP _COPCTL.Bits.WCOP#define COPCTL_CR _COPCTL.MergedBits.grpCR/*** CTCTL - CRG Test Control Register; 0x0000003E ***/typedef union {byte Byte;struct {byte TCTL0 :1; /* CRG Test Control Bit 0 */byte TCTL1 :1; /* CRG Test Control Bit 1 */byte TCTL2 :1; /* CRG Test Control Bit 2 */byte TCTL3 :1; /* CRG Test Control Bit 3 */byte TCTL4 :1; /* CRG Test Control Bit 4 */byte TCTL5 :1; /* CRG Test Control Bit 5 */byte TCTL6 :1; /* CRG Test Control Bit 6 */byte TCTL7 :1; /* CRG Test Control Bit 7 */} Bits;struct {byte grpTCTL :8;} MergedBits;} CTCTLSTR;extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);#define CTCTL _CTCTL.Byte#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/typedef union {byte Byte;struct {byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} ARMCOPSTR;extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);#define ARMCOP _ARMCOP.Byte#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/typedef union {byte Byte;struct {byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */} Bits;struct {byte grpIOS :8;} MergedBits;} TIOSSTR;extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);#define TIOS _TIOS.Byte#define TIOS_IOS0 _TIOS.Bits.IOS0#define TIOS_IOS1 _TIOS.Bits.IOS1#define TIOS_IOS2 _TIOS.Bits.IOS2#define TIOS_IOS3 _TIOS.Bits.IOS3#define TIOS_IOS4 _TIOS.Bits.IOS4#define TIOS_IOS5 _TIOS.Bits.IOS5#define TIOS_IOS6 _TIOS.Bits.IOS6#define TIOS_IOS7 _TIOS.Bits.IOS7#define TIOS_IOS _TIOS.MergedBits.grpIOS/*** CFORC - Timer Compare Force Register; 0x00000041 ***/typedef union {byte Byte;struct {byte FOC0 :1; /* Force Output Compare Action for Channel 0 */byte FOC1 :1; /* Force Output Compare Action for Channel 1 */byte FOC2 :1; /* Force Output Compare Action for Channel 2 */byte FOC3 :1; /* Force Output Compare Action for Channel 3 */byte FOC4 :1; /* Force Output Compare Action for Channel 4 */byte FOC5 :1; /* Force Output Compare Action for Channel 5 */byte FOC6 :1; /* Force Output Compare Action for Channel 6 */byte FOC7 :1; /* Force Output Compare Action for Channel 7 */} Bits;struct {byte grpFOC :8;} MergedBits;} CFORCSTR;extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);#define CFORC _CFORC.Byte#define CFORC_FOC0 _CFORC.Bits.FOC0#define CFORC_FOC1 _CFORC.Bits.FOC1#define CFORC_FOC2 _CFORC.Bits.FOC2#define CFORC_FOC3 _CFORC.Bits.FOC3#define CFORC_FOC4 _CFORC.Bits.FOC4#define CFORC_FOC5 _CFORC.Bits.FOC5#define CFORC_FOC6 _CFORC.Bits.FOC6#define CFORC_FOC7 _CFORC.Bits.FOC7#define CFORC_FOC _CFORC.MergedBits.grpFOC/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/typedef union {byte Byte;struct {byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */} Bits;struct {byte grpOC7M :8;} MergedBits;} OC7MSTR;extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);#define OC7M _OC7M.Byte#define OC7M_OC7M0 _OC7M.Bits.OC7M0#define OC7M_OC7M1 _OC7M.Bits.OC7M1#define OC7M_OC7M2 _OC7M.Bits.OC7M2#define OC7M_OC7M3 _OC7M.Bits.OC7M3#define OC7M_OC7M4 _OC7M.Bits.OC7M4#define OC7M_OC7M5 _OC7M.Bits.OC7M5#define OC7M_OC7M6 _OC7M.Bits.OC7M6#define OC7M_OC7M7 _OC7M.Bits.OC7M7#define OC7M_OC7M _OC7M.MergedBits.grpOC7M/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/typedef union {byte Byte;struct {byte OC7D0 :1; /* Output Compare 7 Bit 0 */byte OC7D1 :1; /* Output Compare 7 Bit 1 */byte OC7D2 :1; /* Output Compare 7 Bit 2 */byte OC7D3 :1; /* Output Compare 7 Bit 3 */byte OC7D4 :1; /* Output Compare 7 Bit 4 */byte OC7D5 :1; /* Output Compare 7 Bit 5 */byte OC7D6 :1; /* Output Compare 7 Bit 6 */byte OC7D7 :1; /* Output Compare 7 Bit 7 */} Bits;struct {byte grpOC7D :8;} MergedBits;} OC7DSTR;extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);#define OC7D _OC7D.Byte#define OC7D_OC7D0 _OC7D.Bits.OC7D0#define OC7D_OC7D1 _OC7D.Bits.OC7D1#define OC7D_OC7D2 _OC7D.Bits.OC7D2#define OC7D_OC7D3 _OC7D.Bits.OC7D3#define OC7D_OC7D4 _OC7D.Bits.OC7D4#define OC7D_OC7D5 _OC7D.Bits.OC7D5#define OC7D_OC7D6 _OC7D.Bits.OC7D6#define OC7D_OC7D7 _OC7D.Bits.OC7D7#define OC7D_OC7D _OC7D.MergedBits.grpOC7D/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte TFFCA :1; /* Timer Fast Flag Clear All */byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */byte TSWAI :1; /* Timer Module Stops While in Wait */byte TEN :1; /* Timer Enable */} Bits;} TSCR1STR;extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);#define TSCR1 _TSCR1.Byte#define TSCR1_TFFCA _TSCR1.Bits.TFFCA#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ#define TSCR1_TSWAI _TSCR1.Bits.TSWAI#define TSCR1_TEN _TSCR1.Bits.TEN/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/typedef union {byte Byte;struct {byte TOV0 :1; /* Toggle On Overflow Bit 0 */byte TOV1 :1; /* Toggle On Overflow Bit 1 */byte TOV2 :1; /* Toggle On Overflow Bit 2 */byte TOV3 :1; /* Toggle On Overflow Bit 3 */byte TOV4 :1; /* Toggle On Overflow Bit 4 */byte TOV5 :1; /* Toggle On Overflow Bit 5 */byte TOV6 :1; /* Toggle On Overflow Bit 6 */byte TOV7 :1; /* Toggle On Overflow Bit 7 */} Bits;struct {byte grpTOV :8;} MergedBits;} TTOVSTR;extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);#define TTOV _TTOV.Byte#define TTOV_TOV0 _TTOV.Bits.TOV0#define TTOV_TOV1 _TTOV.Bits.TOV1#define TTOV_TOV2 _TTOV.Bits.TOV2#define TTOV_TOV3 _TTOV.Bits.TOV3#define TTOV_TOV4 _TTOV.Bits.TOV4#define TTOV_TOV5 _TTOV.Bits.TOV5#define TTOV_TOV6 _TTOV.Bits.TOV6#define TTOV_TOV7 _TTOV.Bits.TOV7#define TTOV_TOV _TTOV.MergedBits.grpTOV/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/typedef union {byte Byte;struct {byte OL4 :1; /* Output Level Bit 4 */byte OM4 :1; /* Output Mode Bit 4 */byte OL5 :1; /* Output Level Bit 5 */byte OM5 :1; /* Output Mode Bit 5 */byte OL6 :1; /* Output Level Bit 6 */byte OM6 :1; /* Output Mode Bit 6 */byte OL7 :1; /* Output Level Bit 7 */byte OM7 :1; /* Output Mode Bit 7 */} Bits;} TCTL1STR;extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);#define TCTL1 _TCTL1.Byte#define TCTL1_OL4 _TCTL1.Bits.OL4#define TCTL1_OM4 _TCTL1.Bits.OM4#define TCTL1_OL5 _TCTL1.Bits.OL5#define TCTL1_OM5 _TCTL1.Bits.OM5#define TCTL1_OL6 _TCTL1.Bits.OL6#define TCTL1_OM6 _TCTL1.Bits.OM6#define TCTL1_OL7 _TCTL1.Bits.OL7#define TCTL1_OM7 _TCTL1.Bits.OM7/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/typedef union {byte Byte;struct {byte OL0 :1; /* Output Level Bit 0 */byte OM0 :1; /* Output Mode Bit 0 */byte OL1 :1; /* Output Level Bit 1 */byte OM1 :1; /* Output Mode Bit 1 */byte OL2 :1; /* Output Level Bit 2 */byte OM2 :1; /* Output Mode Bit 2 */byte OL3 :1; /* Output Level Bit 3 */byte OM3 :1; /* Output Mode Bit 3 */} Bits;} TCTL2STR;extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);#define TCTL2 _TCTL2.Byte#define TCTL2_OL0 _TCTL2.Bits.OL0#define TCTL2_OM0 _TCTL2.Bits.OM0#define TCTL2_OL1 _TCTL2.Bits.OL1#define TCTL2_OM1 _TCTL2.Bits.OM1#define TCTL2_OL2 _TCTL2.Bits.OL2#define TCTL2_OM2 _TCTL2.Bits.OM2#define TCTL2_OL3 _TCTL2.Bits.OL3#define TCTL2_OM3 _TCTL2.Bits.OM3/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/typedef union {byte Byte;struct {byte EDG4A :1; /* Input Capture Edge Control 4A */byte EDG4B :1; /* Input Capture Edge Control 4B */byte EDG5A :1; /* Input Capture Edge Control 5A */byte EDG5B :1; /* Input Capture Edge Control 5B */byte EDG6A :1; /* Input Capture Edge Control 6A */byte EDG6B :1; /* Input Capture Edge Control 6B */byte EDG7A :1; /* Input Capture Edge Control 7A */byte EDG7B :1; /* Input Capture Edge Control 7B */} Bits;} TCTL3STR;extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);#define TCTL3 _TCTL3.Byte#define TCTL3_EDG4A _TCTL3.Bits.EDG4A#define TCTL3_EDG4B _TCTL3.Bits.EDG4B#define TCTL3_EDG5A _TCTL3.Bits.EDG5A#define TCTL3_EDG5B _TCTL3.Bits.EDG5B#define TCTL3_EDG6A _TCTL3.Bits.EDG6A#define TCTL3_EDG6B _TCTL3.Bits.EDG6B#define TCTL3_EDG7A _TCTL3.Bits.EDG7A#define TCTL3_EDG7B _TCTL3.Bits.EDG7B/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/typedef union {byte Byte;struct {byte EDG0A :1; /* Input Capture Edge Control 0A */byte EDG0B :1; /* Input Capture Edge Control 0B */byte EDG1A :1; /* Input Capture Edge Control 1A */byte EDG1B :1; /* Input Capture Edge Control 1B */byte EDG2A :1; /* Input Capture Edge Control 2A */byte EDG2B :1; /* Input Capture Edge Control 2B */byte EDG3A :1; /* Input Capture Edge Control 3A */byte EDG3B :1; /* Input Capture Edge Control 3B */} Bits;} TCTL4STR;extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);#define TCTL4 _TCTL4.Byte#define TCTL4_EDG0A _TCTL4.Bits.EDG0A#define TCTL4_EDG0B _TCTL4.Bits.EDG0B#define TCTL4_EDG1A _TCTL4.Bits.EDG1A#define TCTL4_EDG1B _TCTL4.Bits.EDG1B#define TCTL4_EDG2A _TCTL4.Bits.EDG2A#define TCTL4_EDG2B _TCTL4.Bits.EDG2B#define TCTL4_EDG3A _TCTL4.Bits.EDG3A#define TCTL4_EDG3B _TCTL4.Bits.EDG3B/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/typedef union {byte Byte;struct {byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */} Bits;} TIESTR;extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);#define TIE _TIE.Byte#define TIE_C0I _TIE.Bits.C0I#define TIE_C1I _TIE.Bits.C1I#define TIE_C2I _TIE.Bits.C2I#define TIE_C3I _TIE.Bits.C3I#define TIE_C4I _TIE.Bits.C4I#define TIE_C5I _TIE.Bits.C5I#define TIE_C6I _TIE.Bits.C6I#define TIE_C7I _TIE.Bits.C7I/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/typedef union {byte Byte;struct {byte PR0 :1; /* Timer Prescaler Select Bit 0 */byte PR1 :1; /* Timer Prescaler Select Bit 1 */byte PR2 :1; /* Timer Prescaler Select Bit 2 */byte TCRE :1; /* Timer Counter Reset Enable */byte :1;byte :1;byte :1;byte TOI :1; /* Timer Overflow Interrupt Enable */} Bits;struct {byte grpPR :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} TSCR2STR;extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);#define TSCR2 _TSCR2.Byte#define TSCR2_PR0 _TSCR2.Bits.PR0#define TSCR2_PR1 _TSCR2.Bits.PR1#define TSCR2_PR2 _TSCR2.Bits.PR2#define TSCR2_TCRE _TSCR2.Bits.TCRE#define TSCR2_TOI _TSCR2.Bits.TOI#define TSCR2_PR _TSCR2.MergedBits.grpPR/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/typedef union {byte Byte;struct {byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */} Bits;} TFLG1STR;extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);#define TFLG1 _TFLG1.Byte#define TFLG1_C0F _TFLG1.Bits.C0F#define TFLG1_C1F _TFLG1.Bits.C1F#define TFLG1_C2F _TFLG1.Bits.C2F#define TFLG1_C3F _TFLG1.Bits.C3F#define TFLG1_C4F _TFLG1.Bits.C4F#define TFLG1_C5F _TFLG1.Bits.C5F#define TFLG1_C6F _TFLG1.Bits.C6F#define TFLG1_C7F _TFLG1.Bits.C7F/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte TOF :1; /* Timer Overflow Flag */} Bits;} TFLG2STR;extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);#define TFLG2 _TFLG2.Byte#define TFLG2_TOF _TFLG2.Bits.TOF/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/typedef union {byte Byte;struct {byte PAI :1; /* Pulse Accumulator Input Interrupt enable */byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */byte CLK0 :1; /* Clock Select Bit 0 */byte CLK1 :1; /* Clock Select Bit 1 */byte PEDGE :1; /* Pulse Accumulator Edge Control */byte PAMOD :1; /* Pulse Accumulator Mode */byte PAEN :1; /* Pulse Accumulator A System Enable */byte :1;} Bits;struct {byte :1;byte :1;byte grpCLK :2;byte :1;byte :1;byte :1;byte :1;} MergedBits;} PACTLSTR;extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);#define PACTL _PACTL.Byte#define PACTL_PAI _PACTL.Bits.PAI#define PACTL_PAOVI _PACTL.Bits.PAOVI#define PACTL_CLK0 _PACTL.Bits.CLK0#define PACTL_CLK1 _PACTL.Bits.CLK1#define PACTL_PEDGE _PACTL.Bits.PEDGE#define PACTL_PAMOD _PACTL.Bits.PAMOD#define PACTL_PAEN _PACTL.Bits.PAEN#define PACTL_CLK _PACTL.MergedBits.grpCLK/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/typedef union {byte Byte;struct {byte PAIF :1; /* Pulse Accumulator Input edge Flag */byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;} PAFLGSTR;extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);#define PAFLG _PAFLG.Byte#define PAFLG_PAIF _PAFLG.Bits.PAIF#define PAFLG_PAOVF _PAFLG.Bits.PAOVF/*** ATDSTAT0 - A/D Status Register 0; 0x00000086 ***/typedef union {byte Byte;struct {byte CC0 :1; /* Conversion Counter 0 */byte CC1 :1; /* Conversion Counter 1 */byte CC2 :1; /* Conversion Counter 2 */byte :1;byte FIFOR :1; /* FIFO Over Run Flag */byte ETORF :1; /* External Trigger Overrun Flag */byte :1;byte SCF :1; /* Sequence Complete Flag */} Bits;struct {byte grpCC :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} ATDSTAT0STR;extern volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086);#define ATDSTAT0 _ATDSTAT0.Byte#define ATDSTAT0_CC0 _ATDSTAT0.Bits.CC0#define ATDSTAT0_CC1 _ATDSTAT0.Bits.CC1#define ATDSTAT0_CC2 _ATDSTAT0.Bits.CC2#define ATDSTAT0_FIFOR _ATDSTAT0.Bits.FIFOR#define ATDSTAT0_ETORF _ATDSTAT0.Bits.ETORF#define ATDSTAT0_SCF _ATDSTAT0.Bits.SCF#define ATDSTAT0_CC _ATDSTAT0.MergedBits.grpCC/*** ATDSTAT1 - A/D Status Register 1; 0x0000008B ***/typedef union {byte Byte;struct {byte CCF0 :1; /* Conversion Complete Flag 0 */byte CCF1 :1; /* Conversion Complete Flag 1 */byte CCF2 :1; /* Conversion Complete Flag 2 */byte CCF3 :1; /* Conversion Complete Flag 3 */byte CCF4 :1; /* Conversion Complete Flag 4 */byte CCF5 :1; /* Conversion Complete Flag 5 */byte CCF6 :1; /* Conversion Complete Flag 6 */byte CCF7 :1; /* Conversion Complete Flag 7 */} Bits;struct {byte grpCCF :8;} MergedBits;} ATDSTAT1STR;extern volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B);#define ATDSTAT1 _ATDSTAT1.Byte#define ATDSTAT1_CCF0 _ATDSTAT1.Bits.CCF0#define ATDSTAT1_CCF1 _ATDSTAT1.Bits.CCF1#define ATDSTAT1_CCF2 _ATDSTAT1.Bits.CCF2#define ATDSTAT1_CCF3 _ATDSTAT1.Bits.CCF3#define ATDSTAT1_CCF4 _ATDSTAT1.Bits.CCF4#define ATDSTAT1_CCF5 _ATDSTAT1.Bits.CCF5#define ATDSTAT1_CCF6 _ATDSTAT1.Bits.CCF6#define ATDSTAT1_CCF7 _ATDSTAT1.Bits.CCF7#define ATDSTAT1_CCF _ATDSTAT1.MergedBits.grpCCF/*** ATDDIEN - ATD Input Enable Mask Register; 0x0000008D ***/typedef union {byte Byte;struct {byte BIT0 :1; /* Disable/Enable digital input buffer */byte BIT1 :1; /* Disable/Enable digital input buffer */byte BIT2 :1; /* Disable/Enable digital input buffer */byte BIT3 :1; /* Disable/Enable digital input buffer */byte BIT4 :1; /* Disable/Enable digital input buffer */byte BIT5 :1; /* Disable/Enable digital input buffer */byte BIT6 :1; /* Disable/Enable digital input buffer */byte BIT7 :1; /* Disable/Enable digital input buffer */} Bits;struct {byte grpBIT :8;} MergedBits;} ATDDIENSTR;extern volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008D);#define ATDDIEN _ATDDIEN.Byte#define ATDDIEN_BIT0 _ATDDIEN.Bits.BIT0#define ATDDIEN_BIT1 _ATDDIEN.Bits.BIT1#define ATDDIEN_BIT2 _ATDDIEN.Bits.BIT2#define ATDDIEN_BIT3 _ATDDIEN.Bits.BIT3#define ATDDIEN_BIT4 _ATDDIEN.Bits.BIT4#define ATDDIEN_BIT5 _ATDDIEN.Bits.BIT5#define ATDDIEN_BIT6 _ATDDIEN.Bits.BIT6#define ATDDIEN_BIT7 _ATDDIEN.Bits.BIT7#define ATDDIEN_BIT _ATDDIEN.MergedBits.grpBIT/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/typedef union {byte Byte;struct {byte BIT0 :1; /* AN0 */byte BIT1 :1; /* AN1 */byte BIT2 :1; /* AN2 */byte BIT3 :1; /* AN3 */byte BIT4 :1; /* AN4 */byte BIT5 :1; /* AN5 */byte BIT6 :1; /* AN6 */byte BIT7 :1; /* AN7 */} Bits;struct {byte grpBIT :8;} MergedBits;} PORTAD0STR;extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);#define PORTAD0 _PORTAD0.Byte#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT/*** SCICR1 - SCI Control Register 1; 0x000000CA ***/typedef union {byte Byte;struct {byte PT :1; /* Parity Type Bit */byte PE :1; /* Parity Enable Bit */byte ILT :1; /* Idle Line Type Bit */byte WAKE :1; /* Wakeup Condition Bit */byte M :1; /* Data Format Mode Bit */byte RSRC :1; /* Receiver Source Bit */byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */byte LOOPS :1; /* Loop Select Bit */} Bits;} SCICR1STR;extern volatile SCICR1STR _SCICR1 @(REG_BASE + 0x000000CA);#define SCICR1 _SCICR1.Byte#define SCICR1_PT _SCICR1.Bits.PT#define SCICR1_PE _SCICR1.Bits.PE#define SCICR1_ILT _SCICR1.Bits.ILT#define SCICR1_WAKE _SCICR1.Bits.WAKE#define SCICR1_M _SCICR1.Bits.M#define SCICR1_RSRC _SCICR1.Bits.RSRC#define SCICR1_SCISWAI _SCICR1.Bits.SCISWAI#define SCICR1_LOOPS _SCICR1.Bits.LOOPS/*** SCICR2 - SCI Control Register 2; 0x000000CB ***/typedef union {byte Byte;struct {byte SBK :1; /* Send Break Bit */byte RWU :1; /* Receiver Wakeup Bit */byte RE :1; /* Receiver Enable Bit */byte TE :1; /* Transmitter Enable Bit */byte ILIE :1; /* Idle Line Interrupt Enable Bit */byte RIE :1; /* Receiver Full Interrupt Enable Bit */byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */byte SCTIE :1; /* Transmitter Interrupt Enable Bit */} Bits;} SCICR2STR;extern volatile SCICR2STR _SCICR2 @(REG_BASE + 0x000000CB);#define SCICR2 _SCICR2.Byte#define SCICR2_SBK _SCICR2.Bits.SBK#define SCICR2_RWU _SCICR2.Bits.RWU#define SCICR2_RE _SCICR2.Bits.RE#define SCICR2_TE _SCICR2.Bits.TE#define SCICR2_ILIE _SCICR2.Bits.ILIE#define SCICR2_RIE _SCICR2.Bits.RIE#define SCICR2_TCIE _SCICR2.Bits.TCIE#define SCICR2_SCTIE _SCICR2.Bits.SCTIE/*** SCISR1 - SCI Status Register 1; 0x000000CC ***/typedef union {byte Byte;struct {byte PF :1; /* Parity Error Flag */byte FE :1; /* Framing Error Flag */byte NF :1; /* Noise Flag */byte OR :1; /* Overrun Flag */byte IDLE :1; /* Idle Line Flag */byte RDRF :1; /* Receive Data Register Full Flag */byte TC :1; /* Transmit Complete Flag */byte TDRE :1; /* Transmit Data Register Empty Flag */} Bits;} SCISR1STR;extern volatile SCISR1STR _SCISR1 @(REG_BASE + 0x000000CC);#define SCISR1 _SCISR1.Byte#define SCISR1_PF _SCISR1.Bits.PF#define SCISR1_FE _SCISR1.Bits.FE#define SCISR1_NF _SCISR1.Bits.NF#define SCISR1_OR _SCISR1.Bits.OR#define SCISR1_IDLE _SCISR1.Bits.IDLE#define SCISR1_RDRF _SCISR1.Bits.RDRF#define SCISR1_TC _SCISR1.Bits.TC#define SCISR1_TDRE _SCISR1.Bits.TDRE/*** SCISR2 - SCI Status Register 2; 0x000000CD ***/typedef union {byte Byte;struct {byte RAF :1; /* Receiver Active Flag */byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */byte BRK13 :1; /* Break Transmit character length */byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;} SCISR2STR;extern volatile SCISR2STR _SCISR2 @(REG_BASE + 0x000000CD);#define SCISR2 _SCISR2.Byte#define SCISR2_RAF _SCISR2.Bits.RAF#define SCISR2_TXDIR _SCISR2.Bits.TXDIR#define SCISR2_BRK13 _SCISR2.Bits.BRK13/*** SCIDRH - SCI Data Register High; 0x000000CE ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte T8 :1; /* Transmit Bit 8 */byte R8 :1; /* Received Bit 8 */} Bits;} SCIDRHSTR;extern volatile SCIDRHSTR _SCIDRH @(REG_BASE + 0x000000CE);#define SCIDRH _SCIDRH.Byte#define SCIDRH_T8 _SCIDRH.Bits.T8#define SCIDRH_R8 _SCIDRH.Bits.R8/*** SCIDRL - SCI Data Register Low; 0x000000CF ***/typedef union {byte Byte;struct {byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */} Bits;} SCIDRLSTR;extern volatile SCIDRLSTR _SCIDRL @(REG_BASE + 0x000000CF);#define SCIDRL _SCIDRL.Byte#define SCIDRL_R0_T0 _SCIDRL.Bits.R0_T0#define SCIDRL_R1_T1 _SCIDRL.Bits.R1_T1#define SCIDRL_R2_T2 _SCIDRL.Bits.R2_T2#define SCIDRL_R3_T3 _SCIDRL.Bits.R3_T3#define SCIDRL_R4_T4 _SCIDRL.Bits.R4_T4#define SCIDRL_R5_T5 _SCIDRL.Bits.R5_T5#define SCIDRL_R6_T6 _SCIDRL.Bits.R6_T6#define SCIDRL_R7_T7 _SCIDRL.Bits.R7_T7/*** SPICR1 - SPI Control Register; 0x000000D8 ***/typedef union {byte Byte;struct {byte LSBFE :1; /* SPI LSB-First Enable */byte SSOE :1; /* Slave Select Output Enable */byte CPHA :1; /* SPI Clock Phase Bit */byte CPOL :1; /* SPI Clock Polarity Bit */byte MSTR :1; /* SPI Master/Slave Mode Select Bit */byte SPTIE :1; /* SPI Transmit Interrupt Enable */byte SPE :1; /* SPI System Enable Bit */byte SPIE :1; /* SPI Interrupt Enable Bit */} Bits;} SPICR1STR;extern volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8);#define SPICR1 _SPICR1.Byte#define SPICR1_LSBFE _SPICR1.Bits.LSBFE#define SPICR1_SSOE _SPICR1.Bits.SSOE#define SPICR1_CPHA _SPICR1.Bits.CPHA#define SPICR1_CPOL _SPICR1.Bits.CPOL#define SPICR1_MSTR _SPICR1.Bits.MSTR#define SPICR1_SPTIE _SPICR1.Bits.SPTIE#define SPICR1_SPE _SPICR1.Bits.SPE#define SPICR1_SPIE _SPICR1.Bits.SPIE/*** SPICR2 - SPI Control Register 2; 0x000000D9 ***/typedef union {byte Byte;struct {byte SPC0 :1; /* Serial Pin Control Bit 0 */byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */byte :1;byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */byte MODFEN :1; /* Mode Fault Enable Bit */byte :1;byte :1;byte :1;} Bits;} SPICR2STR;extern volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9);#define SPICR2 _SPICR2.Byte#define SPICR2_SPC0 _SPICR2.Bits.SPC0#define SPICR2_SPISWAI _SPICR2.Bits.SPISWAI#define SPICR2_BIDIROE _SPICR2.Bits.BIDIROE#define SPICR2_MODFEN _SPICR2.Bits.MODFEN/*** SPIBR - SPI Baud Rate Register; 0x000000DA ***/typedef union {byte Byte;struct {byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */byte :1;byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */byte :1;} Bits;struct {byte grpSPR :3;byte :1;byte grpSPPR :3;byte :1;} MergedBits;} SPIBRSTR;extern volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA);#define SPIBR _SPIBR.Byte#define SPIBR_SPR0 _SPIBR.Bits.SPR0#define SPIBR_SPR1 _SPIBR.Bits.SPR1#define SPIBR_SPR2 _SPIBR.Bits.SPR2#define SPIBR_SPPR0 _SPIBR.Bits.SPPR0#define SPIBR_SPPR1 _SPIBR.Bits.SPPR1#define SPIBR_SPPR2 _SPIBR.Bits.SPPR2#define SPIBR_SPR _SPIBR.MergedBits.grpSPR#define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR/*** SPISR - SPI Status Register; 0x000000DB ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte MODF :1; /* Mode Fault Flag */byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */byte :1;byte SPIF :1; /* SPIF Receive Interrupt Flag */} Bits;} SPISRSTR;extern volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB);#define SPISR _SPISR.Byte#define SPISR_MODF _SPISR.Bits.MODF#define SPISR_SPTEF _SPISR.Bits.SPTEF#define SPISR_SPIF _SPISR.Bits.SPIF/*** SPIDR - SPI Data Register; 0x000000DD ***/typedef union {byte Byte;struct {byte grpBIT :8;} MergedBits;} SPIDRSTR;extern volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD);#define SPIDR _SPIDR.Byte#define SPIDR_BIT _SPIDR.MergedBits.grpBIT/*** PWME - PWM Enable Register; 0x000000E0 ***/typedef union {byte Byte;struct {byte PWME0 :1; /* Pulse Width Channel 0 Enable */byte PWME1 :1; /* Pulse Width Channel 1 Enable */byte PWME2 :1; /* Pulse Width Channel 2 Enable */byte PWME3 :1; /* Pulse Width Channel 3 Enable */byte PWME4 :1; /* Pulse Width Channel 4 Enable */byte PWME5 :1; /* Pulse Width Channel 5 Enable */byte PWME6 :1; /* Pulse Width Channel 6 Enable */byte PWME7 :1; /* Pulse Width Channel 7 Enable */} Bits;struct {byte grpPWME :8;} MergedBits;} PWMESTR;extern volatile PWMESTR _PWME @(REG_BASE + 0x000000E0);#define PWME _PWME.Byte#define PWME_PWME0 _PWME.Bits.PWME0#define PWME_PWME1 _PWME.Bits.PWME1#define PWME_PWME2 _PWME.Bits.PWME2#define PWME_PWME3 _PWME.Bits.PWME3#define PWME_PWME4 _PWME.Bits.PWME4#define PWME_PWME5 _PWME.Bits.PWME5#define PWME_PWME6 _PWME.Bits.PWME6#define PWME_PWME7 _PWME.Bits.PWME7#define PWME_PWME _PWME.MergedBits.grpPWME/*** PWMPOL - PWM Polarity Register; 0x000000E1 ***/typedef union {byte Byte;struct {byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */} Bits;struct {byte grpPPOL :8;} MergedBits;} PWMPOLSTR;extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1);#define PWMPOL _PWMPOL.Byte#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL/*** PWMCLK - PWM Clock Select Register; 0x000000E2 ***/typedef union {byte Byte;struct {byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */} Bits;struct {byte grpPCLK :8;} MergedBits;} PWMCLKSTR;extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2);#define PWMCLK _PWMCLK.Byte#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000E3 ***/typedef union {byte Byte;struct {byte PCKA0 :1; /* Prescaler Select for Clock A 0 */byte PCKA1 :1; /* Prescaler Select for Clock A 1 */byte PCKA2 :1; /* Prescaler Select for Clock A 2 */byte :1;byte PCKB0 :1; /* Prescaler Select for Clock B 0 */byte PCKB1 :1; /* Prescaler Select for Clock B 1 */byte PCKB2 :1; /* Prescaler Select for Clock B 2 */byte :1;} Bits;struct {byte grpPCKA :3;byte :1;byte grpPCKB :3;byte :1;} MergedBits;} PWMPRCLKSTR;extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3);#define PWMPRCLK _PWMPRCLK.Byte#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB/*** PWMCAE - PWM Center Align Enable Register; 0x000000E4 ***/typedef union {byte Byte;struct {byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */} Bits;struct {byte grpCAE :8;} MergedBits;} PWMCAESTR;extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4);#define PWMCAE _PWMCAE.Byte#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE/*** PWMCTL - PWM Control Register; 0x000000E5 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */byte PSWAI :1; /* PWM Stops in Wait Mode */byte CON01 :1; /* Concatenate channels 0 and 1 */byte CON23 :1; /* Concatenate channels 2 and 3 */byte CON45 :1; /* Concatenate channels 4 and 5 */byte CON67 :1; /* Concatenate channels 6 and 7 */} Bits;} PWMCTLSTR;extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5);#define PWMCTL _PWMCTL.Byte#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI#define PWMCTL_CON01 _PWMCTL.Bits.CON01#define PWMCTL_CON23 _PWMCTL.Bits.CON23#define PWMCTL_CON45 _PWMCTL.Bits.CON45#define PWMCTL_CON67 _PWMCTL.Bits.CON67/*** PWMSCLA - PWM Scale A Register; 0x000000E8 ***/typedef union {byte Byte;struct {byte BIT0 :1; /* PWM Scale A Bit 0 */byte BIT1 :1; /* PWM Scale A Bit 1 */byte BIT2 :1; /* PWM Scale A Bit 2 */byte BIT3 :1; /* PWM Scale A Bit 3 */byte BIT4 :1; /* PWM Scale A Bit 4 */byte BIT5 :1; /* PWM Scale A Bit 5 */byte BIT6 :1; /* PWM Scale A Bit 6 */byte BIT7 :1; /* PWM Scale A Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} PWMSCLASTR;extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8);#define PWMSCLA _PWMSCLA.Byte#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT/*** PWMSCLB - PWM Scale B Register; 0x000000E9 ***/typedef union {byte Byte;struct {byte BIT0 :1; /* PWM Scale B Bit 0 */byte BIT1 :1; /* PWM Scale B Bit 1 */byte BIT2 :1; /* PWM Scale B Bit 2 */byte BIT3 :1; /* PWM Scale B Bit 3 */byte BIT4 :1; /* PWM Scale B Bit 4 */byte BIT5 :1; /* PWM Scale B Bit 5 */byte BIT6 :1; /* PWM Scale B Bit 6 */byte BIT7 :1; /* PWM Scale B Bit 7 */} Bits;struct {byte grpBIT :8;} MergedBits;} PWMSCLBSTR;extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9);#define PWMSCLB _PWMSCLB.Byte#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT/*** PWMSDN - PWM Shutdown Register; 0x000000FE ***/typedef union {byte Byte;struct {byte PWM7ENA :1; /* PWM emergency shutdown Enable */byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */byte PWM7IN :1; /* PWM channel 7 input status */byte :1;byte PWMLVL :1; /* PWM shutdown output Level */byte PWMRSTRT :1; /* PWM Restart */byte PWMIE :1; /* PWM Interrupt Enable */byte PWMIF :1; /* PWM Interrupt Flag */} Bits;} PWMSDNSTR;extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE);#define PWMSDN _PWMSDN.Byte#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/typedef union {byte Byte;struct {byte FDIV0 :1; /* Flash Clock Divider Bit 0 */byte FDIV1 :1; /* Flash Clock Divider Bit 1 */byte FDIV2 :1; /* Flash Clock Divider Bit 2 */byte FDIV3 :1; /* Flash Clock Divider Bit 3 */byte FDIV4 :1; /* Flash Clock Divider Bit 4 */byte FDIV5 :1; /* Flash Clock Divider Bit 5 */byte PRDIV8 :1; /* Enable Prescaler by 8 */byte FDIVLD :1; /* Flash Clock Divider Loaded */} Bits;struct {byte grpFDIV :6;byte grpPRDIV_8 :1;byte :1;} MergedBits;} FCLKDIVSTR;extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);#define FCLKDIV _FCLKDIV.Byte#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV/*** FSEC - Flash Security Register; 0x00000101 ***/typedef union {byte Byte;struct {byte SEC0 :1; /* Memory security bit 0 */byte SEC1 :1; /* Memory security bit 1 */byte NV2 :1; /* Non Volatile flag bit 2 */byte NV3 :1; /* Non Volatile flag bit 3 */byte NV4 :1; /* Non Volatile flag bit 4 */byte NV5 :1; /* Non Volatile flag bit 5 */byte NV6 :1; /* Non Volatile flag bit 6 */byte KEYEN :1; /* Enable backdoor key to security */} Bits;struct {byte grpSEC :2;byte grpNV_2 :5;byte :1;} MergedBits;} FSECSTR;extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);#define FSEC _FSEC.Byte#define FSEC_SEC0 _FSEC.Bits.SEC0#define FSEC_SEC1 _FSEC.Bits.SEC1#define FSEC_NV2 _FSEC.Bits.NV2#define FSEC_NV3 _FSEC.Bits.NV3#define FSEC_NV4 _FSEC.Bits.NV4#define FSEC_NV5 _FSEC.Bits.NV5#define FSEC_NV6 _FSEC.Bits.NV6#define FSEC_KEYEN _FSEC.Bits.KEYEN#define FSEC_SEC _FSEC.MergedBits.grpSEC#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2#define FSEC_NV FSEC_NV_2/*** FCNFG - Flash Configuration Register; 0x00000103 ***/typedef union {byte Byte;struct {byte BKSEL0 :1; /* Register bank select 0 */byte BKSEL1 :1; /* Register bank select 1 */byte :1;byte :1;byte :1;byte KEYACC :1; /* Enable Security Key Writing */byte CCIE :1; /* Command Complete Interrupt Enable */byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */} Bits;struct {byte grpBKSEL :2;byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} FCNFGSTR;extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);#define FCNFG _FCNFG.Byte#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1#define FCNFG_KEYACC _FCNFG.Bits.KEYACC#define FCNFG_CCIE _FCNFG.Bits.CCIE#define FCNFG_CBEIE _FCNFG.Bits.CBEIE#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL/*** FPROT - Flash Protection Register; 0x00000104 ***/typedef union {byte Byte;struct {byte FPLS0 :1; /* Flash Protection Lower Address size 0 */byte FPLS1 :1; /* Flash Protection Lower Address size 1 */byte FPLDIS :1; /* Flash Protection Lower address range disable */byte FPHS0 :1; /* Flash Protection Higher address size 0 */byte FPHS1 :1; /* Flash Protection Higher address size 1 */byte FPHDIS :1; /* Flash Protection Higher address range disable */byte NV6 :1; /* Non Volatile Flag Bit */byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */} Bits;struct {byte grpFPLS :2;byte :1;byte grpFPHS :2;byte :1;byte grpNV_6 :1;byte :1;} MergedBits;} FPROTSTR;extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);#define FPROT _FPROT.Byte#define FPROT_FPLS0 _FPROT.Bits.FPLS0#define FPROT_FPLS1 _FPROT.Bits.FPLS1#define FPROT_FPLDIS _FPROT.Bits.FPLDIS#define FPROT_FPHS0 _FPROT.Bits.FPHS0#define FPROT_FPHS1 _FPROT.Bits.FPHS1#define FPROT_FPHDIS _FPROT.Bits.FPHDIS#define FPROT_NV6 _FPROT.Bits.NV6#define FPROT_FPOPEN _FPROT.Bits.FPOPEN#define FPROT_FPLS _FPROT.MergedBits.grpFPLS#define FPROT_FPHS _FPROT.MergedBits.grpFPHS/*** FSTAT - Flash Status Register; 0x00000105 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte BLANK :1; /* Blank Verify Flag */byte :1;byte ACCERR :1; /* Access error */byte PVIOL :1; /* Protection violation */byte CCIF :1; /* Command Complete Interrupt Flag */byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */} Bits;} FSTATSTR;extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);#define FSTAT _FSTAT.Byte#define FSTAT_BLANK _FSTAT.Bits.BLANK#define FSTAT_ACCERR _FSTAT.Bits.ACCERR#define FSTAT_PVIOL _FSTAT.Bits.PVIOL#define FSTAT_CCIF _FSTAT.Bits.CCIF#define FSTAT_CBEIF _FSTAT.Bits.CBEIF/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/typedef union {byte Byte;struct {byte CMDB0 :1; /* NVM User Mode Command Bit 0 */byte :1;byte CMDB2 :1; /* NVM User Mode Command Bit 2 */byte :1;byte :1;byte CMDB5 :1; /* NVM User Mode Command Bit 5 */byte CMDB6 :1; /* NVM User Mode Command Bit 6 */byte :1;} Bits;struct {byte grpCMDB :1;byte :1;byte grpCMDB_2 :1;byte :1;byte :1;byte grpCMDB_5 :2;byte :1;} MergedBits;} FCMDSTR;extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);#define FCMD _FCMD.Byte#define FCMD_CMDB0 _FCMD.Bits.CMDB0#define FCMD_CMDB2 _FCMD.Bits.CMDB2#define FCMD_CMDB5 _FCMD.Bits.CMDB5#define FCMD_CMDB6 _FCMD.Bits.CMDB6#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5#define FCMD_CMDB FCMD_CMDB_5/*** CANCTL0 - MSCAN Control 0 Register; 0x00000140 ***/typedef union {byte Byte;struct {byte INITRQ :1; /* Initialization Mode Request */byte SLPRQ :1; /* Sleep Mode Request */byte WUPE :1; /* Wake-Up Enable */byte TIME :1; /* Timer Enable */byte SYNCH :1; /* Synchronized Status */byte CSWAI :1; /* CAN Stops in Wait Mode */byte RXACT :1; /* Receiver Active Status */byte RXFRM :1; /* Received Frame Flag */} Bits;} CANCTL0STR;extern volatile CANCTL0STR _CANCTL0 @(REG_BASE + 0x00000140);#define CANCTL0 _CANCTL0.Byte#define CANCTL0_INITRQ _CANCTL0.Bits.INITRQ#define CANCTL0_SLPRQ _CANCTL0.Bits.SLPRQ#define CANCTL0_WUPE _CANCTL0.Bits.WUPE#define CANCTL0_TIME _CANCTL0.Bits.TIME#define CANCTL0_SYNCH _CANCTL0.Bits.SYNCH#define CANCTL0_CSWAI _CANCTL0.Bits.CSWAI#define CANCTL0_RXACT _CANCTL0.Bits.RXACT#define CANCTL0_RXFRM _CANCTL0.Bits.RXFRM/*** CANCTL1 - MSCAN Control 1 Register; 0x00000141 ***/typedef union {byte Byte;struct {byte INITAK :1; /* Initialization Mode Acknowledge */byte SLPAK :1; /* Sleep Mode Acknowledge */byte WUPM :1; /* Wake-Up Mode */byte :1;byte LISTEN :1; /* Listen Only Mode */byte LOOPB :1; /* Loop Back Self Test Mode */byte CLKSRC :1; /* MSCAN Clock Source */byte CANE :1; /* MSCAN Enable */} Bits;} CANCTL1STR;extern volatile CANCTL1STR _CANCTL1 @(REG_BASE + 0x00000141);#define CANCTL1 _CANCTL1.Byte#define CANCTL1_INITAK _CANCTL1.Bits.INITAK#define CANCTL1_SLPAK _CANCTL1.Bits.SLPAK#define CANCTL1_WUPM _CANCTL1.Bits.WUPM#define CANCTL1_LISTEN _CANCTL1.Bits.LISTEN#define CANCTL1_LOOPB _CANCTL1.Bits.LOOPB#define CANCTL1_CLKSRC _CANCTL1.Bits.CLKSRC#define CANCTL1_CANE _CANCTL1.Bits.CANE/*** CANBTR0 - MSCAN Bus Timing Register 0; 0x00000142 ***/typedef union {byte Byte;struct {byte BRP0 :1; /* Baud Rate Prescaler 0 */byte BRP1 :1; /* Baud Rate Prescaler 1 */byte BRP2 :1; /* Baud Rate Prescaler 2 */byte BRP3 :1; /* Baud Rate Prescaler 3 */byte BRP4 :1; /* Baud Rate Prescaler 4 */byte BRP5 :1; /* Baud Rate Prescaler 5 */byte SJW0 :1; /* Synchronization Jump Width 0 */byte SJW1 :1; /* Synchronization Jump Width 1 */} Bits;struct {byte grpBRP :6;byte grpSJW :2;} MergedBits;} CANBTR0STR;extern volatile CANBTR0STR _CANBTR0 @(REG_BASE + 0x00000142);#define CANBTR0 _CANBTR0.Byte#define CANBTR0_BRP0 _CANBTR0.Bits.BRP0#define CANBTR0_BRP1 _CANBTR0.Bits.BRP1#define CANBTR0_BRP2 _CANBTR0.Bits.BRP2#define CANBTR0_BRP3 _CANBTR0.Bits.BRP3#define CANBTR0_BRP4 _CANBTR0.Bits.BRP4#define CANBTR0_BRP5 _CANBTR0.Bits.BRP5#define CANBTR0_SJW0 _CANBTR0.Bits.SJW0#define CANBTR0_SJW1 _CANBTR0.Bits.SJW1#define CANBTR0_BRP _CANBTR0.MergedBits.grpBRP#define CANBTR0_SJW _CANBTR0.MergedBits.grpSJW/*** CANBTR1 - MSCAN Bus Timing Register 1; 0x00000143 ***/typedef union {byte Byte;struct {byte TSEG10 :1; /* Time Segment 1 */byte TSEG11 :1; /* Time Segment 1 */byte TSEG12 :1; /* Time Segment 1 */byte TSEG13 :1; /* Time Segment 1 */byte TSEG20 :1; /* Time Segment 2 */byte TSEG21 :1; /* Time Segment 2 */byte TSEG22 :1; /* Time Segment 2 */byte SAMP :1; /* Sampling */} Bits;struct {byte grpTSEG_10 :4;byte grpTSEG_20 :3;byte :1;} MergedBits;} CANBTR1STR;extern volatile CANBTR1STR _CANBTR1 @(REG_BASE + 0x00000143);#define CANBTR1 _CANBTR1.Byte#define CANBTR1_TSEG10 _CANBTR1.Bits.TSEG10#define CANBTR1_TSEG11 _CANBTR1.Bits.TSEG11#define CANBTR1_TSEG12 _CANBTR1.Bits.TSEG12#define CANBTR1_TSEG13 _CANBTR1.Bits.TSEG13#define CANBTR1_TSEG20 _CANBTR1.Bits.TSEG20#define CANBTR1_TSEG21 _CANBTR1.Bits.TSEG21#define CANBTR1_TSEG22 _CANBTR1.Bits.TSEG22#define CANBTR1_SAMP _CANBTR1.Bits.SAMP#define CANBTR1_TSEG_10 _CANBTR1.MergedBits.grpTSEG_10#define CANBTR1_TSEG_20 _CANBTR1.MergedBits.grpTSEG_20#define CANBTR1_TSEG CANBTR1_TSEG_10/*** CANRFLG - MSCAN Receiver Flag Register; 0x00000144 ***/typedef union {byte Byte;struct {byte RXF :1; /* Receive Buffer Full */byte OVRIF :1; /* Overrun Interrupt Flag */byte TSTAT0 :1; /* Transmitter Status Bit 0 */byte TSTAT1 :1; /* Transmitter Status Bit 1 */byte RSTAT0 :1; /* Receiver Status Bit 0 */byte RSTAT1 :1; /* Receiver Status Bit 1 */byte CSCIF :1; /* CAN Status Change Interrupt Flag */byte WUPIF :1; /* Wake-up Interrupt Flag */} Bits;struct {byte :1;byte :1;byte grpTSTAT :2;byte grpRSTAT :2;byte :1;byte :1;} MergedBits;} CANRFLGSTR;extern volatile CANRFLGSTR _CANRFLG @(REG_BASE + 0x00000144);#define CANRFLG _CANRFLG.Byte#define CANRFLG_RXF _CANRFLG.Bits.RXF#define CANRFLG_OVRIF _CANRFLG.Bits.OVRIF#define CANRFLG_TSTAT0 _CANRFLG.Bits.TSTAT0#define CANRFLG_TSTAT1 _CANRFLG.Bits.TSTAT1#define CANRFLG_RSTAT0 _CANRFLG.Bits.RSTAT0#define CANRFLG_RSTAT1 _CANRFLG.Bits.RSTAT1#define CANRFLG_CSCIF _CANRFLG.Bits.CSCIF#define CANRFLG_WUPIF _CANRFLG.Bits.WUPIF#define CANRFLG_TSTAT _CANRFLG.MergedBits.grpTSTAT#define CANRFLG_RSTAT _CANRFLG.MergedBits.grpRSTAT/*** CANRIER - MSCAN Receiver Interrupt Enable Register; 0x00000145 ***/typedef union {byte Byte;struct {byte RXFIE :1; /* Receiver Full Interrupt Enable */byte OVRIE :1; /* Overrun Interrupt Enable */byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */byte RSTATE0 :1; /* Receiver Status Change Enable 0 */byte RSTATE1 :1; /* Receiver Status Change Enable 1 */byte CSCIE :1; /* CAN Status Change Interrupt Enable */byte WUPIE :1; /* Wake-up Interrupt Enable */} Bits;struct {byte :1;byte :1;byte grpTSTATE :2;byte grpRSTATE :2;byte :1;byte :1;} MergedBits;} CANRIERSTR;extern volatile CANRIERSTR _CANRIER @(REG_BASE + 0x00000145);#define CANRIER _CANRIER.Byte#define CANRIER_RXFIE _CANRIER.Bits.RXFIE#define CANRIER_OVRIE _CANRIER.Bits.OVRIE#define CANRIER_TSTATE0 _CANRIER.Bits.TSTATE0#define CANRIER_TSTATE1 _CANRIER.Bits.TSTATE1#define CANRIER_RSTATE0 _CANRIER.Bits.RSTATE0#define CANRIER_RSTATE1 _CANRIER.Bits.RSTATE1#define CANRIER_CSCIE _CANRIER.Bits.CSCIE#define CANRIER_WUPIE _CANRIER.Bits.WUPIE#define CANRIER_TSTATE _CANRIER.MergedBits.grpTSTATE#define CANRIER_RSTATE _CANRIER.MergedBits.grpRSTATE/*** CANTFLG - MSCAN Transmitter Flag Register; 0x00000146 ***/typedef union {byte Byte;struct {byte TXE0 :1; /* Transmitter Buffer Empty 0 */byte TXE1 :1; /* Transmitter Buffer Empty 1 */byte TXE2 :1; /* Transmitter Buffer Empty 2 */byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpTXE :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} CANTFLGSTR;extern volatile CANTFLGSTR _CANTFLG @(REG_BASE + 0x00000146);#define CANTFLG _CANTFLG.Byte#define CANTFLG_TXE0 _CANTFLG.Bits.TXE0#define CANTFLG_TXE1 _CANTFLG.Bits.TXE1#define CANTFLG_TXE2 _CANTFLG.Bits.TXE2#define CANTFLG_TXE _CANTFLG.MergedBits.grpTXE/*** CANTIER - MSCAN Transmitter Interrupt Enable Register; 0x00000147 ***/typedef union {byte Byte;struct {byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpTXEIE :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} CANTIERSTR;extern volatile CANTIERSTR _CANTIER @(REG_BASE + 0x00000147);#define CANTIER _CANTIER.Byte#define CANTIER_TXEIE0 _CANTIER.Bits.TXEIE0#define CANTIER_TXEIE1 _CANTIER.Bits.TXEIE1#define CANTIER_TXEIE2 _CANTIER.Bits.TXEIE2#define CANTIER_TXEIE _CANTIER.MergedBits.grpTXEIE/*** CANTARQ - MSCAN Transmitter Message Abort Request; 0x00000148 ***/typedef union {byte Byte;struct {byte ABTRQ0 :1; /* Abort Request 0 */byte ABTRQ1 :1; /* Abort Request 1 */byte ABTRQ2 :1; /* Abort Request 2 */byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpABTRQ :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} CANTARQSTR;extern volatile CANTARQSTR _CANTARQ @(REG_BASE + 0x00000148);#define CANTARQ _CANTARQ.Byte#define CANTARQ_ABTRQ0 _CANTARQ.Bits.ABTRQ0#define CANTARQ_ABTRQ1 _CANTARQ.Bits.ABTRQ1#define CANTARQ_ABTRQ2 _CANTARQ.Bits.ABTRQ2#define CANTARQ_ABTRQ _CANTARQ.MergedBits.grpABTRQ/*** CANTAAK - MSCAN Transmitter Message Abort Control; 0x00000149 ***/typedef union {byte Byte;struct {byte ABTAK0 :1; /* Abort Acknowledge 0 */byte ABTAK1 :1; /* Abort Acknowledge 1 */byte ABTAK2 :1; /* Abort Acknowledge 2 */byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpABTAK :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} CANTAAKSTR;extern volatile CANTAAKSTR _CANTAAK @(REG_BASE + 0x00000149);#define CANTAAK _CANTAAK.Byte#define CANTAAK_ABTAK0 _CANTAAK.Bits.ABTAK0#define CANTAAK_ABTAK1 _CANTAAK.Bits.ABTAK1#define CANTAAK_ABTAK2 _CANTAAK.Bits.ABTAK2#define CANTAAK_ABTAK _CANTAAK.MergedBits.grpABTAK/*** CANTBSEL - MSCAN Transmit Buffer Selection; 0x0000014A ***/typedef union {byte Byte;struct {byte TX0 :1; /* Transmit Buffer Select 0 */byte TX1 :1; /* Transmit Buffer Select 1 */byte TX2 :1; /* Transmit Buffer Select 2 */byte :1;byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpTX :3;byte :1;byte :1;byte :1;byte :1;byte :1;} MergedBits;} CANTBSELSTR;extern volatile CANTBSELSTR _CANTBSEL @(REG_BASE + 0x0000014A);#define CANTBSEL _CANTBSEL.Byte#define CANTBSEL_TX0 _CANTBSEL.Bits.TX0#define CANTBSEL_TX1 _CANTBSEL.Bits.TX1#define CANTBSEL_TX2 _CANTBSEL.Bits.TX2#define CANTBSEL_TX _CANTBSEL.MergedBits.grpTX/*** CANIDAC - MSCAN Identifier Acceptance Control Register; 0x0000014B ***/typedef union {byte Byte;struct {byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */byte :1;byte IDAM0 :1; /* Identifier Acceptance Mode 0 */byte IDAM1 :1; /* Identifier Acceptance Mode 1 */byte :1;byte :1;} Bits;struct {byte grpIDHIT :3;byte :1;byte grpIDAM :2;byte :1;byte :1;} MergedBits;} CANIDACSTR;extern volatile CANIDACSTR _CANIDAC @(REG_BASE + 0x0000014B);#define CANIDAC _CANIDAC.Byte#define CANIDAC_IDHIT0 _CANIDAC.Bits.IDHIT0#define CANIDAC_IDHIT1 _CANIDAC.Bits.IDHIT1#define CANIDAC_IDHIT2 _CANIDAC.Bits.IDHIT2#define CANIDAC_IDAM0 _CANIDAC.Bits.IDAM0#define CANIDAC_IDAM1 _CANIDAC.Bits.IDAM1#define CANIDAC_IDHIT _CANIDAC.MergedBits.grpIDHIT#define CANIDAC_IDAM _CANIDAC.MergedBits.grpIDAM/*** CANRXERR - MSCAN Receive Error Counter Register; 0x0000014E ***/typedef union {byte Byte;struct {byte RXERR0 :1; /* Bit 0 */byte RXERR1 :1; /* Bit 1 */byte RXERR2 :1; /* Bit 2 */byte RXERR3 :1; /* Bit 3 */byte RXERR4 :1; /* Bit 4 */byte RXERR5 :1; /* Bit 5 */byte RXERR6 :1; /* Bit 6 */byte RXERR7 :1; /* Bit 7 */} Bits;struct {byte grpRXERR :8;} MergedBits;} CANRXERRSTR;extern volatile CANRXERRSTR _CANRXERR @(REG_BASE + 0x0000014E);#define CANRXERR _CANRXERR.Byte#define CANRXERR_RXERR0 _CANRXERR.Bits.RXERR0#define CANRXERR_RXERR1 _CANRXERR.Bits.RXERR1#define CANRXERR_RXERR2 _CANRXERR.Bits.RXERR2#define CANRXERR_RXERR3 _CANRXERR.Bits.RXERR3#define CANRXERR_RXERR4 _CANRXERR.Bits.RXERR4#define CANRXERR_RXERR5 _CANRXERR.Bits.RXERR5#define CANRXERR_RXERR6 _CANRXERR.Bits.RXERR6#define CANRXERR_RXERR7 _CANRXERR.Bits.RXERR7#define CANRXERR_RXERR _CANRXERR.MergedBits.grpRXERR/*** CANTXERR - MSCAN Transmit Error Counter Register; 0x0000014F ***/typedef union {byte Byte;struct {byte TXERR0 :1; /* Bit 0 */byte TXERR1 :1; /* Bit 1 */byte TXERR2 :1; /* Bit 2 */byte TXERR3 :1; /* Bit 3 */byte TXERR4 :1; /* Bit 4 */byte TXERR5 :1; /* Bit 5 */byte TXERR6 :1; /* Bit 6 */byte TXERR7 :1; /* Bit 7 */} Bits;struct {byte grpTXERR :8;} MergedBits;} CANTXERRSTR;extern volatile CANTXERRSTR _CANTXERR @(REG_BASE + 0x0000014F);#define CANTXERR _CANTXERR.Byte#define CANTXERR_TXERR0 _CANTXERR.Bits.TXERR0#define CANTXERR_TXERR1 _CANTXERR.Bits.TXERR1#define CANTXERR_TXERR2 _CANTXERR.Bits.TXERR2#define CANTXERR_TXERR3 _CANTXERR.Bits.TXERR3#define CANTXERR_TXERR4 _CANTXERR.Bits.TXERR4#define CANTXERR_TXERR5 _CANTXERR.Bits.TXERR5#define CANTXERR_TXERR6 _CANTXERR.Bits.TXERR6#define CANTXERR_TXERR7 _CANTXERR.Bits.TXERR7#define CANTXERR_TXERR _CANTXERR.MergedBits.grpTXERR/*** CANIDAR0 - MSCAN Identifier Acceptance Register 0; 0x00000150 ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR0STR;extern volatile CANIDAR0STR _CANIDAR0 @(REG_BASE + 0x00000150);#define CANIDAR0 _CANIDAR0.Byte#define CANIDAR0_AC0 _CANIDAR0.Bits.AC0#define CANIDAR0_AC1 _CANIDAR0.Bits.AC1#define CANIDAR0_AC2 _CANIDAR0.Bits.AC2#define CANIDAR0_AC3 _CANIDAR0.Bits.AC3#define CANIDAR0_AC4 _CANIDAR0.Bits.AC4#define CANIDAR0_AC5 _CANIDAR0.Bits.AC5#define CANIDAR0_AC6 _CANIDAR0.Bits.AC6#define CANIDAR0_AC7 _CANIDAR0.Bits.AC7#define CANIDAR0_AC _CANIDAR0.MergedBits.grpAC/*** CANIDAR1 - MSCAN Identifier Acceptance Register 1; 0x00000151 ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR1STR;extern volatile CANIDAR1STR _CANIDAR1 @(REG_BASE + 0x00000151);#define CANIDAR1 _CANIDAR1.Byte#define CANIDAR1_AC0 _CANIDAR1.Bits.AC0#define CANIDAR1_AC1 _CANIDAR1.Bits.AC1#define CANIDAR1_AC2 _CANIDAR1.Bits.AC2#define CANIDAR1_AC3 _CANIDAR1.Bits.AC3#define CANIDAR1_AC4 _CANIDAR1.Bits.AC4#define CANIDAR1_AC5 _CANIDAR1.Bits.AC5#define CANIDAR1_AC6 _CANIDAR1.Bits.AC6#define CANIDAR1_AC7 _CANIDAR1.Bits.AC7#define CANIDAR1_AC _CANIDAR1.MergedBits.grpAC/*** CANIDAR2 - MSCAN Identifier Acceptance Register 2; 0x00000152 ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR2STR;extern volatile CANIDAR2STR _CANIDAR2 @(REG_BASE + 0x00000152);#define CANIDAR2 _CANIDAR2.Byte#define CANIDAR2_AC0 _CANIDAR2.Bits.AC0#define CANIDAR2_AC1 _CANIDAR2.Bits.AC1#define CANIDAR2_AC2 _CANIDAR2.Bits.AC2#define CANIDAR2_AC3 _CANIDAR2.Bits.AC3#define CANIDAR2_AC4 _CANIDAR2.Bits.AC4#define CANIDAR2_AC5 _CANIDAR2.Bits.AC5#define CANIDAR2_AC6 _CANIDAR2.Bits.AC6#define CANIDAR2_AC7 _CANIDAR2.Bits.AC7#define CANIDAR2_AC _CANIDAR2.MergedBits.grpAC/*** CANIDAR3 - MSCAN Identifier Acceptance Register 3; 0x00000153 ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR3STR;extern volatile CANIDAR3STR _CANIDAR3 @(REG_BASE + 0x00000153);#define CANIDAR3 _CANIDAR3.Byte#define CANIDAR3_AC0 _CANIDAR3.Bits.AC0#define CANIDAR3_AC1 _CANIDAR3.Bits.AC1#define CANIDAR3_AC2 _CANIDAR3.Bits.AC2#define CANIDAR3_AC3 _CANIDAR3.Bits.AC3#define CANIDAR3_AC4 _CANIDAR3.Bits.AC4#define CANIDAR3_AC5 _CANIDAR3.Bits.AC5#define CANIDAR3_AC6 _CANIDAR3.Bits.AC6#define CANIDAR3_AC7 _CANIDAR3.Bits.AC7#define CANIDAR3_AC _CANIDAR3.MergedBits.grpAC/*** CANIDMR0 - MSCAN Identifier Mask Register 0; 0x00000154 ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR0STR;extern volatile CANIDMR0STR _CANIDMR0 @(REG_BASE + 0x00000154);#define CANIDMR0 _CANIDMR0.Byte#define CANIDMR0_AM0 _CANIDMR0.Bits.AM0#define CANIDMR0_AM1 _CANIDMR0.Bits.AM1#define CANIDMR0_AM2 _CANIDMR0.Bits.AM2#define CANIDMR0_AM3 _CANIDMR0.Bits.AM3#define CANIDMR0_AM4 _CANIDMR0.Bits.AM4#define CANIDMR0_AM5 _CANIDMR0.Bits.AM5#define CANIDMR0_AM6 _CANIDMR0.Bits.AM6#define CANIDMR0_AM7 _CANIDMR0.Bits.AM7#define CANIDMR0_AM _CANIDMR0.MergedBits.grpAM/*** CANIDMR1 - MSCAN Identifier Mask Register 1; 0x00000155 ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR1STR;extern volatile CANIDMR1STR _CANIDMR1 @(REG_BASE + 0x00000155);#define CANIDMR1 _CANIDMR1.Byte#define CANIDMR1_AM0 _CANIDMR1.Bits.AM0#define CANIDMR1_AM1 _CANIDMR1.Bits.AM1#define CANIDMR1_AM2 _CANIDMR1.Bits.AM2#define CANIDMR1_AM3 _CANIDMR1.Bits.AM3#define CANIDMR1_AM4 _CANIDMR1.Bits.AM4#define CANIDMR1_AM5 _CANIDMR1.Bits.AM5#define CANIDMR1_AM6 _CANIDMR1.Bits.AM6#define CANIDMR1_AM7 _CANIDMR1.Bits.AM7#define CANIDMR1_AM _CANIDMR1.MergedBits.grpAM/*** CANIDMR2 - MSCAN Identifier Mask Register 2; 0x00000156 ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR2STR;extern volatile CANIDMR2STR _CANIDMR2 @(REG_BASE + 0x00000156);#define CANIDMR2 _CANIDMR2.Byte#define CANIDMR2_AM0 _CANIDMR2.Bits.AM0#define CANIDMR2_AM1 _CANIDMR2.Bits.AM1#define CANIDMR2_AM2 _CANIDMR2.Bits.AM2#define CANIDMR2_AM3 _CANIDMR2.Bits.AM3#define CANIDMR2_AM4 _CANIDMR2.Bits.AM4#define CANIDMR2_AM5 _CANIDMR2.Bits.AM5#define CANIDMR2_AM6 _CANIDMR2.Bits.AM6#define CANIDMR2_AM7 _CANIDMR2.Bits.AM7#define CANIDMR2_AM _CANIDMR2.MergedBits.grpAM/*** CANIDMR3 - MSCAN Identifier Mask Register 3; 0x00000157 ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR3STR;extern volatile CANIDMR3STR _CANIDMR3 @(REG_BASE + 0x00000157);#define CANIDMR3 _CANIDMR3.Byte#define CANIDMR3_AM0 _CANIDMR3.Bits.AM0#define CANIDMR3_AM1 _CANIDMR3.Bits.AM1#define CANIDMR3_AM2 _CANIDMR3.Bits.AM2#define CANIDMR3_AM3 _CANIDMR3.Bits.AM3#define CANIDMR3_AM4 _CANIDMR3.Bits.AM4#define CANIDMR3_AM5 _CANIDMR3.Bits.AM5#define CANIDMR3_AM6 _CANIDMR3.Bits.AM6#define CANIDMR3_AM7 _CANIDMR3.Bits.AM7#define CANIDMR3_AM _CANIDMR3.MergedBits.grpAM/*** CANIDAR4 - MSCAN Identifier Acceptance Register 4; 0x00000158 ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR4STR;extern volatile CANIDAR4STR _CANIDAR4 @(REG_BASE + 0x00000158);#define CANIDAR4 _CANIDAR4.Byte#define CANIDAR4_AC0 _CANIDAR4.Bits.AC0#define CANIDAR4_AC1 _CANIDAR4.Bits.AC1#define CANIDAR4_AC2 _CANIDAR4.Bits.AC2#define CANIDAR4_AC3 _CANIDAR4.Bits.AC3#define CANIDAR4_AC4 _CANIDAR4.Bits.AC4#define CANIDAR4_AC5 _CANIDAR4.Bits.AC5#define CANIDAR4_AC6 _CANIDAR4.Bits.AC6#define CANIDAR4_AC7 _CANIDAR4.Bits.AC7#define CANIDAR4_AC _CANIDAR4.MergedBits.grpAC/*** CANIDAR5 - MSCAN Identifier Acceptance Register 5; 0x00000159 ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR5STR;extern volatile CANIDAR5STR _CANIDAR5 @(REG_BASE + 0x00000159);#define CANIDAR5 _CANIDAR5.Byte#define CANIDAR5_AC0 _CANIDAR5.Bits.AC0#define CANIDAR5_AC1 _CANIDAR5.Bits.AC1#define CANIDAR5_AC2 _CANIDAR5.Bits.AC2#define CANIDAR5_AC3 _CANIDAR5.Bits.AC3#define CANIDAR5_AC4 _CANIDAR5.Bits.AC4#define CANIDAR5_AC5 _CANIDAR5.Bits.AC5#define CANIDAR5_AC6 _CANIDAR5.Bits.AC6#define CANIDAR5_AC7 _CANIDAR5.Bits.AC7#define CANIDAR5_AC _CANIDAR5.MergedBits.grpAC/*** CANIDAR6 - MSCAN Identifier Acceptance Register 6; 0x0000015A ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR6STR;extern volatile CANIDAR6STR _CANIDAR6 @(REG_BASE + 0x0000015A);#define CANIDAR6 _CANIDAR6.Byte#define CANIDAR6_AC0 _CANIDAR6.Bits.AC0#define CANIDAR6_AC1 _CANIDAR6.Bits.AC1#define CANIDAR6_AC2 _CANIDAR6.Bits.AC2#define CANIDAR6_AC3 _CANIDAR6.Bits.AC3#define CANIDAR6_AC4 _CANIDAR6.Bits.AC4#define CANIDAR6_AC5 _CANIDAR6.Bits.AC5#define CANIDAR6_AC6 _CANIDAR6.Bits.AC6#define CANIDAR6_AC7 _CANIDAR6.Bits.AC7#define CANIDAR6_AC _CANIDAR6.MergedBits.grpAC/*** CANIDAR7 - MSCAN Identifier Acceptance Register 7; 0x0000015B ***/typedef union {byte Byte;struct {byte AC0 :1; /* Acceptance Code Bit 0 */byte AC1 :1; /* Acceptance Code Bit 1 */byte AC2 :1; /* Acceptance Code Bit 2 */byte AC3 :1; /* Acceptance Code Bit 3 */byte AC4 :1; /* Acceptance Code Bit 4 */byte AC5 :1; /* Acceptance Code Bit 5 */byte AC6 :1; /* Acceptance Code Bit 6 */byte AC7 :1; /* Acceptance Code Bit 7 */} Bits;struct {byte grpAC :8;} MergedBits;} CANIDAR7STR;extern volatile CANIDAR7STR _CANIDAR7 @(REG_BASE + 0x0000015B);#define CANIDAR7 _CANIDAR7.Byte#define CANIDAR7_AC0 _CANIDAR7.Bits.AC0#define CANIDAR7_AC1 _CANIDAR7.Bits.AC1#define CANIDAR7_AC2 _CANIDAR7.Bits.AC2#define CANIDAR7_AC3 _CANIDAR7.Bits.AC3#define CANIDAR7_AC4 _CANIDAR7.Bits.AC4#define CANIDAR7_AC5 _CANIDAR7.Bits.AC5#define CANIDAR7_AC6 _CANIDAR7.Bits.AC6#define CANIDAR7_AC7 _CANIDAR7.Bits.AC7#define CANIDAR7_AC _CANIDAR7.MergedBits.grpAC/*** CANIDMR4 - MSCAN Identifier Mask Register 4; 0x0000015C ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR4STR;extern volatile CANIDMR4STR _CANIDMR4 @(REG_BASE + 0x0000015C);#define CANIDMR4 _CANIDMR4.Byte#define CANIDMR4_AM0 _CANIDMR4.Bits.AM0#define CANIDMR4_AM1 _CANIDMR4.Bits.AM1#define CANIDMR4_AM2 _CANIDMR4.Bits.AM2#define CANIDMR4_AM3 _CANIDMR4.Bits.AM3#define CANIDMR4_AM4 _CANIDMR4.Bits.AM4#define CANIDMR4_AM5 _CANIDMR4.Bits.AM5#define CANIDMR4_AM6 _CANIDMR4.Bits.AM6#define CANIDMR4_AM7 _CANIDMR4.Bits.AM7#define CANIDMR4_AM _CANIDMR4.MergedBits.grpAM/*** CANIDMR5 - MSCAN Identifier Mask Register 5; 0x0000015D ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR5STR;extern volatile CANIDMR5STR _CANIDMR5 @(REG_BASE + 0x0000015D);#define CANIDMR5 _CANIDMR5.Byte#define CANIDMR5_AM0 _CANIDMR5.Bits.AM0#define CANIDMR5_AM1 _CANIDMR5.Bits.AM1#define CANIDMR5_AM2 _CANIDMR5.Bits.AM2#define CANIDMR5_AM3 _CANIDMR5.Bits.AM3#define CANIDMR5_AM4 _CANIDMR5.Bits.AM4#define CANIDMR5_AM5 _CANIDMR5.Bits.AM5#define CANIDMR5_AM6 _CANIDMR5.Bits.AM6#define CANIDMR5_AM7 _CANIDMR5.Bits.AM7#define CANIDMR5_AM _CANIDMR5.MergedBits.grpAM/*** CANIDMR6 - MSCAN Identifier Mask Register 6; 0x0000015E ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR6STR;extern volatile CANIDMR6STR _CANIDMR6 @(REG_BASE + 0x0000015E);#define CANIDMR6 _CANIDMR6.Byte#define CANIDMR6_AM0 _CANIDMR6.Bits.AM0#define CANIDMR6_AM1 _CANIDMR6.Bits.AM1#define CANIDMR6_AM2 _CANIDMR6.Bits.AM2#define CANIDMR6_AM3 _CANIDMR6.Bits.AM3#define CANIDMR6_AM4 _CANIDMR6.Bits.AM4#define CANIDMR6_AM5 _CANIDMR6.Bits.AM5#define CANIDMR6_AM6 _CANIDMR6.Bits.AM6#define CANIDMR6_AM7 _CANIDMR6.Bits.AM7#define CANIDMR6_AM _CANIDMR6.MergedBits.grpAM/*** CANIDMR7 - MSCAN Identifier Mask Register 7; 0x0000015F ***/typedef union {byte Byte;struct {byte AM0 :1; /* Acceptance Mask Bit 0 */byte AM1 :1; /* Acceptance Mask Bit 1 */byte AM2 :1; /* Acceptance Mask Bit 2 */byte AM3 :1; /* Acceptance Mask Bit 3 */byte AM4 :1; /* Acceptance Mask Bit 4 */byte AM5 :1; /* Acceptance Mask Bit 5 */byte AM6 :1; /* Acceptance Mask Bit 6 */byte AM7 :1; /* Acceptance Mask Bit 7 */} Bits;struct {byte grpAM :8;} MergedBits;} CANIDMR7STR;extern volatile CANIDMR7STR _CANIDMR7 @(REG_BASE + 0x0000015F);#define CANIDMR7 _CANIDMR7.Byte#define CANIDMR7_AM0 _CANIDMR7.Bits.AM0#define CANIDMR7_AM1 _CANIDMR7.Bits.AM1#define CANIDMR7_AM2 _CANIDMR7.Bits.AM2#define CANIDMR7_AM3 _CANIDMR7.Bits.AM3#define CANIDMR7_AM4 _CANIDMR7.Bits.AM4#define CANIDMR7_AM5 _CANIDMR7.Bits.AM5#define CANIDMR7_AM6 _CANIDMR7.Bits.AM6#define CANIDMR7_AM7 _CANIDMR7.Bits.AM7#define CANIDMR7_AM _CANIDMR7.MergedBits.grpAM/*** CANRXIDR0 - MSCAN Receive Identifier Register 0; 0x00000160 ***/typedef union {byte Byte;struct {byte ID21 :1; /* Extended format identifier Bit 21 */byte ID22 :1; /* Extended format identifier Bit 22 */byte ID23 :1; /* Extended format identifier Bit 23 */byte ID24 :1; /* Extended format identifier Bit 24 */byte ID25 :1; /* Extended format identifier Bit 25 */byte ID26 :1; /* Extended format identifier Bit 26 */byte ID27 :1; /* Extended format identifier Bit 27 */byte ID28 :1; /* Extended format identifier Bit 28 */} Bits;struct {byte grpID_21 :8;} MergedBits;} CANRXIDR0STR;extern volatile CANRXIDR0STR _CANRXIDR0 @(REG_BASE + 0x00000160);#define CANRXIDR0 _CANRXIDR0.Byte#define CANRXIDR0_ID21 _CANRXIDR0.Bits.ID21#define CANRXIDR0_ID22 _CANRXIDR0.Bits.ID22#define CANRXIDR0_ID23 _CANRXIDR0.Bits.ID23#define CANRXIDR0_ID24 _CANRXIDR0.Bits.ID24#define CANRXIDR0_ID25 _CANRXIDR0.Bits.ID25#define CANRXIDR0_ID26 _CANRXIDR0.Bits.ID26#define CANRXIDR0_ID27 _CANRXIDR0.Bits.ID27#define CANRXIDR0_ID28 _CANRXIDR0.Bits.ID28#define CANRXIDR0_ID_21 _CANRXIDR0.MergedBits.grpID_21#define CANRXIDR0_ID CANRXIDR0_ID_21/*** CANRXIDR1 - MSCAN Receive Identifier Register 1; 0x00000161 ***/typedef union {byte Byte;struct {byte ID15 :1; /* Extended format identifier Bit 15 */byte ID16 :1; /* Extended format identifier Bit 16 */byte ID17 :1; /* Extended format identifier Bit 17 */byte IDE :1; /* ID Extended */byte SRR :1; /* Substitute Remote Request */byte ID18 :1; /* Extended format identifier Bit 18 */byte ID19 :1; /* Extended format identifier Bit 19 */byte ID20 :1; /* Extended format identifier Bit 20 */} Bits;struct {byte grpID_15 :3;byte :1;byte :1;byte grpID_18 :3;} MergedBits;} CANRXIDR1STR;extern volatile CANRXIDR1STR _CANRXIDR1 @(REG_BASE + 0x00000161);#define CANRXIDR1 _CANRXIDR1.Byte#define CANRXIDR1_ID15 _CANRXIDR1.Bits.ID15#define CANRXIDR1_ID16 _CANRXIDR1.Bits.ID16#define CANRXIDR1_ID17 _CANRXIDR1.Bits.ID17#define CANRXIDR1_IDE _CANRXIDR1.Bits.IDE#define CANRXIDR1_SRR _CANRXIDR1.Bits.SRR#define CANRXIDR1_ID18 _CANRXIDR1.Bits.ID18#define CANRXIDR1_ID19 _CANRXIDR1.Bits.ID19#define CANRXIDR1_ID20 _CANRXIDR1.Bits.ID20#define CANRXIDR1_ID_15 _CANRXIDR1.MergedBits.grpID_15#define CANRXIDR1_ID_18 _CANRXIDR1.MergedBits.grpID_18#define CANRXIDR1_ID CANRXIDR1_ID_15/*** CANRXIDR2 - MSCAN Receive Identifier Register 2; 0x00000162 ***/typedef union {byte Byte;struct {byte ID7 :1; /* Extended format identifier Bit 7 */byte ID8 :1; /* Extended format identifier Bit 8 */byte ID9 :1; /* Extended format identifier Bit 9 */byte ID10 :1; /* Extended format identifier Bit 10 */byte ID11 :1; /* Extended format identifier Bit 11 */byte ID12 :1; /* Extended format identifier Bit 12 */byte ID13 :1; /* Extended format identifier Bit 13 */byte ID14 :1; /* Extended format identifier Bit 14 */} Bits;struct {byte grpID_7 :8;} MergedBits;} CANRXIDR2STR;extern volatile CANRXIDR2STR _CANRXIDR2 @(REG_BASE + 0x00000162);#define CANRXIDR2 _CANRXIDR2.Byte#define CANRXIDR2_ID7 _CANRXIDR2.Bits.ID7#define CANRXIDR2_ID8 _CANRXIDR2.Bits.ID8#define CANRXIDR2_ID9 _CANRXIDR2.Bits.ID9#define CANRXIDR2_ID10 _CANRXIDR2.Bits.ID10#define CANRXIDR2_ID11 _CANRXIDR2.Bits.ID11#define CANRXIDR2_ID12 _CANRXIDR2.Bits.ID12#define CANRXIDR2_ID13 _CANRXIDR2.Bits.ID13#define CANRXIDR2_ID14 _CANRXIDR2.Bits.ID14#define CANRXIDR2_ID_7 _CANRXIDR2.MergedBits.grpID_7#define CANRXIDR2_ID CANRXIDR2_ID_7/*** CANRXIDR3 - MSCAN Receive Identifier Register 3; 0x00000163 ***/typedef union {byte Byte;struct {byte RTR :1; /* Remote Transmission Request */byte ID0 :1; /* Extended format identifier Bit 0 */byte ID1 :1; /* Extended format identifier Bit 1 */byte ID2 :1; /* Extended format identifier Bit 2 */byte ID3 :1; /* Extended format identifier Bit 3 */byte ID4 :1; /* Extended format identifier Bit 4 */byte ID5 :1; /* Extended format identifier Bit 5 */byte ID6 :1; /* Extended format identifier Bit 6 */} Bits;struct {byte :1;byte grpID :7;} MergedBits;} CANRXIDR3STR;extern volatile CANRXIDR3STR _CANRXIDR3 @(REG_BASE + 0x00000163);#define CANRXIDR3 _CANRXIDR3.Byte#define CANRXIDR3_RTR _CANRXIDR3.Bits.RTR#define CANRXIDR3_ID0 _CANRXIDR3.Bits.ID0#define CANRXIDR3_ID1 _CANRXIDR3.Bits.ID1#define CANRXIDR3_ID2 _CANRXIDR3.Bits.ID2#define CANRXIDR3_ID3 _CANRXIDR3.Bits.ID3#define CANRXIDR3_ID4 _CANRXIDR3.Bits.ID4#define CANRXIDR3_ID5 _CANRXIDR3.Bits.ID5#define CANRXIDR3_ID6 _CANRXIDR3.Bits.ID6#define CANRXIDR3_ID _CANRXIDR3.MergedBits.grpID/*** CANRXDSR0 - MSCAN Receive Data Segment Register 0; 0x00000164 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR0STR;extern volatile CANRXDSR0STR _CANRXDSR0 @(REG_BASE + 0x00000164);#define CANRXDSR0 _CANRXDSR0.Byte#define CANRXDSR0_DB0 _CANRXDSR0.Bits.DB0#define CANRXDSR0_DB1 _CANRXDSR0.Bits.DB1#define CANRXDSR0_DB2 _CANRXDSR0.Bits.DB2#define CANRXDSR0_DB3 _CANRXDSR0.Bits.DB3#define CANRXDSR0_DB4 _CANRXDSR0.Bits.DB4#define CANRXDSR0_DB5 _CANRXDSR0.Bits.DB5#define CANRXDSR0_DB6 _CANRXDSR0.Bits.DB6#define CANRXDSR0_DB7 _CANRXDSR0.Bits.DB7#define CANRXDSR0_DB _CANRXDSR0.MergedBits.grpDB/*** CANRXDSR1 - MSCAN Receive Data Segment Register 1; 0x00000165 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR1STR;extern volatile CANRXDSR1STR _CANRXDSR1 @(REG_BASE + 0x00000165);#define CANRXDSR1 _CANRXDSR1.Byte#define CANRXDSR1_DB0 _CANRXDSR1.Bits.DB0#define CANRXDSR1_DB1 _CANRXDSR1.Bits.DB1#define CANRXDSR1_DB2 _CANRXDSR1.Bits.DB2#define CANRXDSR1_DB3 _CANRXDSR1.Bits.DB3#define CANRXDSR1_DB4 _CANRXDSR1.Bits.DB4#define CANRXDSR1_DB5 _CANRXDSR1.Bits.DB5#define CANRXDSR1_DB6 _CANRXDSR1.Bits.DB6#define CANRXDSR1_DB7 _CANRXDSR1.Bits.DB7#define CANRXDSR1_DB _CANRXDSR1.MergedBits.grpDB/*** CANRXDSR2 - MSCAN Receive Data Segment Register 2; 0x00000166 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR2STR;extern volatile CANRXDSR2STR _CANRXDSR2 @(REG_BASE + 0x00000166);#define CANRXDSR2 _CANRXDSR2.Byte#define CANRXDSR2_DB0 _CANRXDSR2.Bits.DB0#define CANRXDSR2_DB1 _CANRXDSR2.Bits.DB1#define CANRXDSR2_DB2 _CANRXDSR2.Bits.DB2#define CANRXDSR2_DB3 _CANRXDSR2.Bits.DB3#define CANRXDSR2_DB4 _CANRXDSR2.Bits.DB4#define CANRXDSR2_DB5 _CANRXDSR2.Bits.DB5#define CANRXDSR2_DB6 _CANRXDSR2.Bits.DB6#define CANRXDSR2_DB7 _CANRXDSR2.Bits.DB7#define CANRXDSR2_DB _CANRXDSR2.MergedBits.grpDB/*** CANRXDSR3 - MSCAN Receive Data Segment Register 3; 0x00000167 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR3STR;extern volatile CANRXDSR3STR _CANRXDSR3 @(REG_BASE + 0x00000167);#define CANRXDSR3 _CANRXDSR3.Byte#define CANRXDSR3_DB0 _CANRXDSR3.Bits.DB0#define CANRXDSR3_DB1 _CANRXDSR3.Bits.DB1#define CANRXDSR3_DB2 _CANRXDSR3.Bits.DB2#define CANRXDSR3_DB3 _CANRXDSR3.Bits.DB3#define CANRXDSR3_DB4 _CANRXDSR3.Bits.DB4#define CANRXDSR3_DB5 _CANRXDSR3.Bits.DB5#define CANRXDSR3_DB6 _CANRXDSR3.Bits.DB6#define CANRXDSR3_DB7 _CANRXDSR3.Bits.DB7#define CANRXDSR3_DB _CANRXDSR3.MergedBits.grpDB/*** CANRXDSR4 - MSCAN Receive Data Segment Register 4; 0x00000168 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR4STR;extern volatile CANRXDSR4STR _CANRXDSR4 @(REG_BASE + 0x00000168);#define CANRXDSR4 _CANRXDSR4.Byte#define CANRXDSR4_DB0 _CANRXDSR4.Bits.DB0#define CANRXDSR4_DB1 _CANRXDSR4.Bits.DB1#define CANRXDSR4_DB2 _CANRXDSR4.Bits.DB2#define CANRXDSR4_DB3 _CANRXDSR4.Bits.DB3#define CANRXDSR4_DB4 _CANRXDSR4.Bits.DB4#define CANRXDSR4_DB5 _CANRXDSR4.Bits.DB5#define CANRXDSR4_DB6 _CANRXDSR4.Bits.DB6#define CANRXDSR4_DB7 _CANRXDSR4.Bits.DB7#define CANRXDSR4_DB _CANRXDSR4.MergedBits.grpDB/*** CANRXDSR5 - MSCAN Receive Data Segment Register 5; 0x00000169 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR5STR;extern volatile CANRXDSR5STR _CANRXDSR5 @(REG_BASE + 0x00000169);#define CANRXDSR5 _CANRXDSR5.Byte#define CANRXDSR5_DB0 _CANRXDSR5.Bits.DB0#define CANRXDSR5_DB1 _CANRXDSR5.Bits.DB1#define CANRXDSR5_DB2 _CANRXDSR5.Bits.DB2#define CANRXDSR5_DB3 _CANRXDSR5.Bits.DB3#define CANRXDSR5_DB4 _CANRXDSR5.Bits.DB4#define CANRXDSR5_DB5 _CANRXDSR5.Bits.DB5#define CANRXDSR5_DB6 _CANRXDSR5.Bits.DB6#define CANRXDSR5_DB7 _CANRXDSR5.Bits.DB7#define CANRXDSR5_DB _CANRXDSR5.MergedBits.grpDB/*** CANRXDSR6 - MSCAN Receive Data Segment Register 6; 0x0000016A ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR6STR;extern volatile CANRXDSR6STR _CANRXDSR6 @(REG_BASE + 0x0000016A);#define CANRXDSR6 _CANRXDSR6.Byte#define CANRXDSR6_DB0 _CANRXDSR6.Bits.DB0#define CANRXDSR6_DB1 _CANRXDSR6.Bits.DB1#define CANRXDSR6_DB2 _CANRXDSR6.Bits.DB2#define CANRXDSR6_DB3 _CANRXDSR6.Bits.DB3#define CANRXDSR6_DB4 _CANRXDSR6.Bits.DB4#define CANRXDSR6_DB5 _CANRXDSR6.Bits.DB5#define CANRXDSR6_DB6 _CANRXDSR6.Bits.DB6#define CANRXDSR6_DB7 _CANRXDSR6.Bits.DB7#define CANRXDSR6_DB _CANRXDSR6.MergedBits.grpDB/*** CANRXDSR7 - MSCAN Receive Data Segment Register 7; 0x0000016B ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANRXDSR7STR;extern volatile CANRXDSR7STR _CANRXDSR7 @(REG_BASE + 0x0000016B);#define CANRXDSR7 _CANRXDSR7.Byte#define CANRXDSR7_DB0 _CANRXDSR7.Bits.DB0#define CANRXDSR7_DB1 _CANRXDSR7.Bits.DB1#define CANRXDSR7_DB2 _CANRXDSR7.Bits.DB2#define CANRXDSR7_DB3 _CANRXDSR7.Bits.DB3#define CANRXDSR7_DB4 _CANRXDSR7.Bits.DB4#define CANRXDSR7_DB5 _CANRXDSR7.Bits.DB5#define CANRXDSR7_DB6 _CANRXDSR7.Bits.DB6#define CANRXDSR7_DB7 _CANRXDSR7.Bits.DB7#define CANRXDSR7_DB _CANRXDSR7.MergedBits.grpDB/*** CANRXDLR - MSCAN Receive Data Length Register; 0x0000016C ***/typedef union {byte Byte;struct {byte DLC0 :1; /* Data Length Code Bit 0 */byte DLC1 :1; /* Data Length Code Bit 1 */byte DLC2 :1; /* Data Length Code Bit 2 */byte DLC3 :1; /* Data Length Code Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpDLC :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} CANRXDLRSTR;extern volatile CANRXDLRSTR _CANRXDLR @(REG_BASE + 0x0000016C);#define CANRXDLR _CANRXDLR.Byte#define CANRXDLR_DLC0 _CANRXDLR.Bits.DLC0#define CANRXDLR_DLC1 _CANRXDLR.Bits.DLC1#define CANRXDLR_DLC2 _CANRXDLR.Bits.DLC2#define CANRXDLR_DLC3 _CANRXDLR.Bits.DLC3#define CANRXDLR_DLC _CANRXDLR.MergedBits.grpDLC/*** CANTXIDR0 - MSCAN Transmit Identifier Register 0; 0x00000170 ***/typedef union {byte Byte;struct {byte ID21 :1; /* Extended format identifier Bit 21 */byte ID22 :1; /* Extended format identifier Bit 22 */byte ID23 :1; /* Extended format identifier Bit 23 */byte ID24 :1; /* Extended format identifier Bit 24 */byte ID25 :1; /* Extended format identifier Bit 25 */byte ID26 :1; /* Extended format identifier Bit 26 */byte ID27 :1; /* Extended format identifier Bit 27 */byte ID28 :1; /* Extended format identifier Bit 28 */} Bits;struct {byte grpID_21 :8;} MergedBits;} CANTXIDR0STR;extern volatile CANTXIDR0STR _CANTXIDR0 @(REG_BASE + 0x00000170);#define CANTXIDR0 _CANTXIDR0.Byte#define CANTXIDR0_ID21 _CANTXIDR0.Bits.ID21#define CANTXIDR0_ID22 _CANTXIDR0.Bits.ID22#define CANTXIDR0_ID23 _CANTXIDR0.Bits.ID23#define CANTXIDR0_ID24 _CANTXIDR0.Bits.ID24#define CANTXIDR0_ID25 _CANTXIDR0.Bits.ID25#define CANTXIDR0_ID26 _CANTXIDR0.Bits.ID26#define CANTXIDR0_ID27 _CANTXIDR0.Bits.ID27#define CANTXIDR0_ID28 _CANTXIDR0.Bits.ID28#define CANTXIDR0_ID_21 _CANTXIDR0.MergedBits.grpID_21#define CANTXIDR0_ID CANTXIDR0_ID_21/*** CANTXIDR1 - MSCAN Transmit Identifier Register 1; 0x00000171 ***/typedef union {byte Byte;struct {byte ID15 :1; /* Extended format identifier Bit 15 */byte ID16 :1; /* Extended format identifier Bit 16 */byte ID17 :1; /* Extended format identifier Bit 17 */byte IDE :1; /* ID Extended */byte SRR :1; /* Substitute Remote Request */byte ID18 :1; /* Extended format identifier Bit 18 */byte ID19 :1; /* Extended format identifier Bit 19 */byte ID20 :1; /* Extended format identifier Bit 20 */} Bits;struct {byte grpID_15 :3;byte :1;byte :1;byte grpID_18 :3;} MergedBits;} CANTXIDR1STR;extern volatile CANTXIDR1STR _CANTXIDR1 @(REG_BASE + 0x00000171);#define CANTXIDR1 _CANTXIDR1.Byte#define CANTXIDR1_ID15 _CANTXIDR1.Bits.ID15#define CANTXIDR1_ID16 _CANTXIDR1.Bits.ID16#define CANTXIDR1_ID17 _CANTXIDR1.Bits.ID17#define CANTXIDR1_IDE _CANTXIDR1.Bits.IDE#define CANTXIDR1_SRR _CANTXIDR1.Bits.SRR#define CANTXIDR1_ID18 _CANTXIDR1.Bits.ID18#define CANTXIDR1_ID19 _CANTXIDR1.Bits.ID19#define CANTXIDR1_ID20 _CANTXIDR1.Bits.ID20#define CANTXIDR1_ID_15 _CANTXIDR1.MergedBits.grpID_15#define CANTXIDR1_ID_18 _CANTXIDR1.MergedBits.grpID_18#define CANTXIDR1_ID CANTXIDR1_ID_15/*** CANTXIDR2 - MSCAN Transmit Identifier Register 2; 0x00000172 ***/typedef union {byte Byte;struct {byte ID7 :1; /* Extended format identifier Bit 7 */byte ID8 :1; /* Extended format identifier Bit 8 */byte ID9 :1; /* Extended format identifier Bit 9 */byte ID10 :1; /* Extended format identifier Bit 10 */byte ID11 :1; /* Extended format identifier Bit 11 */byte ID12 :1; /* Extended format identifier Bit 12 */byte ID13 :1; /* Extended format identifier Bit 13 */byte ID14 :1; /* Extended format identifier Bit 14 */} Bits;struct {byte grpID_7 :8;} MergedBits;} CANTXIDR2STR;extern volatile CANTXIDR2STR _CANTXIDR2 @(REG_BASE + 0x00000172);#define CANTXIDR2 _CANTXIDR2.Byte#define CANTXIDR2_ID7 _CANTXIDR2.Bits.ID7#define CANTXIDR2_ID8 _CANTXIDR2.Bits.ID8#define CANTXIDR2_ID9 _CANTXIDR2.Bits.ID9#define CANTXIDR2_ID10 _CANTXIDR2.Bits.ID10#define CANTXIDR2_ID11 _CANTXIDR2.Bits.ID11#define CANTXIDR2_ID12 _CANTXIDR2.Bits.ID12#define CANTXIDR2_ID13 _CANTXIDR2.Bits.ID13#define CANTXIDR2_ID14 _CANTXIDR2.Bits.ID14#define CANTXIDR2_ID_7 _CANTXIDR2.MergedBits.grpID_7#define CANTXIDR2_ID CANTXIDR2_ID_7/*** CANTXIDR3 - MSCAN Transmit Identifier Register 3; 0x00000173 ***/typedef union {byte Byte;struct {byte RTR :1; /* Remote Transmission Request */byte ID0 :1; /* Extended format identifier Bit 0 */byte ID1 :1; /* Extended format identifier Bit 1 */byte ID2 :1; /* Extended format identifier Bit 2 */byte ID3 :1; /* Extended format identifier Bit 3 */byte ID4 :1; /* Extended format identifier Bit 4 */byte ID5 :1; /* Extended format identifier Bit 5 */byte ID6 :1; /* Extended format identifier Bit 6 */} Bits;struct {byte :1;byte grpID :7;} MergedBits;} CANTXIDR3STR;extern volatile CANTXIDR3STR _CANTXIDR3 @(REG_BASE + 0x00000173);#define CANTXIDR3 _CANTXIDR3.Byte#define CANTXIDR3_RTR _CANTXIDR3.Bits.RTR#define CANTXIDR3_ID0 _CANTXIDR3.Bits.ID0#define CANTXIDR3_ID1 _CANTXIDR3.Bits.ID1#define CANTXIDR3_ID2 _CANTXIDR3.Bits.ID2#define CANTXIDR3_ID3 _CANTXIDR3.Bits.ID3#define CANTXIDR3_ID4 _CANTXIDR3.Bits.ID4#define CANTXIDR3_ID5 _CANTXIDR3.Bits.ID5#define CANTXIDR3_ID6 _CANTXIDR3.Bits.ID6#define CANTXIDR3_ID _CANTXIDR3.MergedBits.grpID/*** CANTXDSR0 - MSCAN Transmit Data Segment Register 0; 0x00000174 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR0STR;extern volatile CANTXDSR0STR _CANTXDSR0 @(REG_BASE + 0x00000174);#define CANTXDSR0 _CANTXDSR0.Byte#define CANTXDSR0_DB0 _CANTXDSR0.Bits.DB0#define CANTXDSR0_DB1 _CANTXDSR0.Bits.DB1#define CANTXDSR0_DB2 _CANTXDSR0.Bits.DB2#define CANTXDSR0_DB3 _CANTXDSR0.Bits.DB3#define CANTXDSR0_DB4 _CANTXDSR0.Bits.DB4#define CANTXDSR0_DB5 _CANTXDSR0.Bits.DB5#define CANTXDSR0_DB6 _CANTXDSR0.Bits.DB6#define CANTXDSR0_DB7 _CANTXDSR0.Bits.DB7#define CANTXDSR0_DB _CANTXDSR0.MergedBits.grpDB/*** CANTXDSR1 - MSCAN Transmit Data Segment Register 1; 0x00000175 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR1STR;extern volatile CANTXDSR1STR _CANTXDSR1 @(REG_BASE + 0x00000175);#define CANTXDSR1 _CANTXDSR1.Byte#define CANTXDSR1_DB0 _CANTXDSR1.Bits.DB0#define CANTXDSR1_DB1 _CANTXDSR1.Bits.DB1#define CANTXDSR1_DB2 _CANTXDSR1.Bits.DB2#define CANTXDSR1_DB3 _CANTXDSR1.Bits.DB3#define CANTXDSR1_DB4 _CANTXDSR1.Bits.DB4#define CANTXDSR1_DB5 _CANTXDSR1.Bits.DB5#define CANTXDSR1_DB6 _CANTXDSR1.Bits.DB6#define CANTXDSR1_DB7 _CANTXDSR1.Bits.DB7#define CANTXDSR1_DB _CANTXDSR1.MergedBits.grpDB/*** CANTXDSR2 - MSCAN Transmit Data Segment Register 2; 0x00000176 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR2STR;extern volatile CANTXDSR2STR _CANTXDSR2 @(REG_BASE + 0x00000176);#define CANTXDSR2 _CANTXDSR2.Byte#define CANTXDSR2_DB0 _CANTXDSR2.Bits.DB0#define CANTXDSR2_DB1 _CANTXDSR2.Bits.DB1#define CANTXDSR2_DB2 _CANTXDSR2.Bits.DB2#define CANTXDSR2_DB3 _CANTXDSR2.Bits.DB3#define CANTXDSR2_DB4 _CANTXDSR2.Bits.DB4#define CANTXDSR2_DB5 _CANTXDSR2.Bits.DB5#define CANTXDSR2_DB6 _CANTXDSR2.Bits.DB6#define CANTXDSR2_DB7 _CANTXDSR2.Bits.DB7#define CANTXDSR2_DB _CANTXDSR2.MergedBits.grpDB/*** CANTXDSR3 - MSCAN Transmit Data Segment Register 3; 0x00000177 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR3STR;extern volatile CANTXDSR3STR _CANTXDSR3 @(REG_BASE + 0x00000177);#define CANTXDSR3 _CANTXDSR3.Byte#define CANTXDSR3_DB0 _CANTXDSR3.Bits.DB0#define CANTXDSR3_DB1 _CANTXDSR3.Bits.DB1#define CANTXDSR3_DB2 _CANTXDSR3.Bits.DB2#define CANTXDSR3_DB3 _CANTXDSR3.Bits.DB3#define CANTXDSR3_DB4 _CANTXDSR3.Bits.DB4#define CANTXDSR3_DB5 _CANTXDSR3.Bits.DB5#define CANTXDSR3_DB6 _CANTXDSR3.Bits.DB6#define CANTXDSR3_DB7 _CANTXDSR3.Bits.DB7#define CANTXDSR3_DB _CANTXDSR3.MergedBits.grpDB/*** CANTXDSR4 - MSCAN Transmit Data Segment Register 4; 0x00000178 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR4STR;extern volatile CANTXDSR4STR _CANTXDSR4 @(REG_BASE + 0x00000178);#define CANTXDSR4 _CANTXDSR4.Byte#define CANTXDSR4_DB0 _CANTXDSR4.Bits.DB0#define CANTXDSR4_DB1 _CANTXDSR4.Bits.DB1#define CANTXDSR4_DB2 _CANTXDSR4.Bits.DB2#define CANTXDSR4_DB3 _CANTXDSR4.Bits.DB3#define CANTXDSR4_DB4 _CANTXDSR4.Bits.DB4#define CANTXDSR4_DB5 _CANTXDSR4.Bits.DB5#define CANTXDSR4_DB6 _CANTXDSR4.Bits.DB6#define CANTXDSR4_DB7 _CANTXDSR4.Bits.DB7#define CANTXDSR4_DB _CANTXDSR4.MergedBits.grpDB/*** CANTXDSR5 - MSCAN Transmit Data Segment Register 5; 0x00000179 ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR5STR;extern volatile CANTXDSR5STR _CANTXDSR5 @(REG_BASE + 0x00000179);#define CANTXDSR5 _CANTXDSR5.Byte#define CANTXDSR5_DB0 _CANTXDSR5.Bits.DB0#define CANTXDSR5_DB1 _CANTXDSR5.Bits.DB1#define CANTXDSR5_DB2 _CANTXDSR5.Bits.DB2#define CANTXDSR5_DB3 _CANTXDSR5.Bits.DB3#define CANTXDSR5_DB4 _CANTXDSR5.Bits.DB4#define CANTXDSR5_DB5 _CANTXDSR5.Bits.DB5#define CANTXDSR5_DB6 _CANTXDSR5.Bits.DB6#define CANTXDSR5_DB7 _CANTXDSR5.Bits.DB7#define CANTXDSR5_DB _CANTXDSR5.MergedBits.grpDB/*** CANTXDSR6 - MSCAN Transmit Data Segment Register 6; 0x0000017A ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR6STR;extern volatile CANTXDSR6STR _CANTXDSR6 @(REG_BASE + 0x0000017A);#define CANTXDSR6 _CANTXDSR6.Byte#define CANTXDSR6_DB0 _CANTXDSR6.Bits.DB0#define CANTXDSR6_DB1 _CANTXDSR6.Bits.DB1#define CANTXDSR6_DB2 _CANTXDSR6.Bits.DB2#define CANTXDSR6_DB3 _CANTXDSR6.Bits.DB3#define CANTXDSR6_DB4 _CANTXDSR6.Bits.DB4#define CANTXDSR6_DB5 _CANTXDSR6.Bits.DB5#define CANTXDSR6_DB6 _CANTXDSR6.Bits.DB6#define CANTXDSR6_DB7 _CANTXDSR6.Bits.DB7#define CANTXDSR6_DB _CANTXDSR6.MergedBits.grpDB/*** CANTXDSR7 - MSCAN Transmit Data Segment Register 7; 0x0000017B ***/typedef union {byte Byte;struct {byte DB0 :1; /* Data Bit 0 */byte DB1 :1; /* Data Bit 1 */byte DB2 :1; /* Data Bit 2 */byte DB3 :1; /* Data Bit 3 */byte DB4 :1; /* Data Bit 4 */byte DB5 :1; /* Data Bit 5 */byte DB6 :1; /* Data Bit 6 */byte DB7 :1; /* Data Bit 7 */} Bits;struct {byte grpDB :8;} MergedBits;} CANTXDSR7STR;extern volatile CANTXDSR7STR _CANTXDSR7 @(REG_BASE + 0x0000017B);#define CANTXDSR7 _CANTXDSR7.Byte#define CANTXDSR7_DB0 _CANTXDSR7.Bits.DB0#define CANTXDSR7_DB1 _CANTXDSR7.Bits.DB1#define CANTXDSR7_DB2 _CANTXDSR7.Bits.DB2#define CANTXDSR7_DB3 _CANTXDSR7.Bits.DB3#define CANTXDSR7_DB4 _CANTXDSR7.Bits.DB4#define CANTXDSR7_DB5 _CANTXDSR7.Bits.DB5#define CANTXDSR7_DB6 _CANTXDSR7.Bits.DB6#define CANTXDSR7_DB7 _CANTXDSR7.Bits.DB7#define CANTXDSR7_DB _CANTXDSR7.MergedBits.grpDB/*** CANTXDLR - MSCAN Transmit Data Length Register; 0x0000017C ***/typedef union {byte Byte;struct {byte DLC0 :1; /* Data Length Code Bit 0 */byte DLC1 :1; /* Data Length Code Bit 1 */byte DLC2 :1; /* Data Length Code Bit 2 */byte DLC3 :1; /* Data Length Code Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpDLC :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} CANTXDLRSTR;extern volatile CANTXDLRSTR _CANTXDLR @(REG_BASE + 0x0000017C);#define CANTXDLR _CANTXDLR.Byte#define CANTXDLR_DLC0 _CANTXDLR.Bits.DLC0#define CANTXDLR_DLC1 _CANTXDLR.Bits.DLC1#define CANTXDLR_DLC2 _CANTXDLR.Bits.DLC2#define CANTXDLR_DLC3 _CANTXDLR.Bits.DLC3#define CANTXDLR_DLC _CANTXDLR.MergedBits.grpDLC/*** CANTXTBPR - MSCAN Transmit Buffer Priority; 0x0000017F ***/typedef union {byte Byte;struct {byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */} Bits;struct {byte grpPRIO :8;} MergedBits;} CANTXTBPRSTR;extern volatile CANTXTBPRSTR _CANTXTBPR @(REG_BASE + 0x0000017F);#define CANTXTBPR _CANTXTBPR.Byte#define CANTXTBPR_PRIO0 _CANTXTBPR.Bits.PRIO0#define CANTXTBPR_PRIO1 _CANTXTBPR.Bits.PRIO1#define CANTXTBPR_PRIO2 _CANTXTBPR.Bits.PRIO2#define CANTXTBPR_PRIO3 _CANTXTBPR.Bits.PRIO3#define CANTXTBPR_PRIO4 _CANTXTBPR.Bits.PRIO4#define CANTXTBPR_PRIO5 _CANTXTBPR.Bits.PRIO5#define CANTXTBPR_PRIO6 _CANTXTBPR.Bits.PRIO6#define CANTXTBPR_PRIO7 _CANTXTBPR.Bits.PRIO7#define CANTXTBPR_PRIO _CANTXTBPR.MergedBits.grpPRIO/*** PTT - Port T I/O Register; 0x00000240 ***/typedef union {byte Byte;struct {byte PTT0 :1; /* Port T Bit 0 */byte PTT1 :1; /* Port T Bit 1 */byte PTT2 :1; /* Port T Bit 2 */byte PTT3 :1; /* Port T Bit 3 */byte PTT4 :1; /* Port T Bit 4 */byte PTT5 :1; /* Port T Bit 5 */byte PTT6 :1; /* Port T Bit 6 */byte PTT7 :1; /* Port T Bit 7 */} Bits;struct {byte grpPTT :8;} MergedBits;} PTTSTR;extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);#define PTT _PTT.Byte#define PTT_PTT0 _PTT.Bits.PTT0#define PTT_PTT1 _PTT.Bits.PTT1#define PTT_PTT2 _PTT.Bits.PTT2#define PTT_PTT3 _PTT.Bits.PTT3#define PTT_PTT4 _PTT.Bits.PTT4#define PTT_PTT5 _PTT.Bits.PTT5#define PTT_PTT6 _PTT.Bits.PTT6#define PTT_PTT7 _PTT.Bits.PTT7#define PTT_PTT _PTT.MergedBits.grpPTT/*** PTIT - Port T Input; 0x00000241 ***/typedef union {byte Byte;struct {byte PTIT0 :1; /* Port T Bit 0 */byte PTIT1 :1; /* Port T Bit 1 */byte PTIT2 :1; /* Port T Bit 2 */byte PTIT3 :1; /* Port T Bit 3 */byte PTIT4 :1; /* Port T Bit 4 */byte PTIT5 :1; /* Port T Bit 5 */byte PTIT6 :1; /* Port T Bit 6 */byte PTIT7 :1; /* Port T Bit 7 */} Bits;struct {byte grpPTIT :8;} MergedBits;} PTITSTR;extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);#define PTIT _PTIT.Byte#define PTIT_PTIT0 _PTIT.Bits.PTIT0#define PTIT_PTIT1 _PTIT.Bits.PTIT1#define PTIT_PTIT2 _PTIT.Bits.PTIT2#define PTIT_PTIT3 _PTIT.Bits.PTIT3#define PTIT_PTIT4 _PTIT.Bits.PTIT4#define PTIT_PTIT5 _PTIT.Bits.PTIT5#define PTIT_PTIT6 _PTIT.Bits.PTIT6#define PTIT_PTIT7 _PTIT.Bits.PTIT7#define PTIT_PTIT _PTIT.MergedBits.grpPTIT/*** DDRT - Port T Data Direction Register; 0x00000242 ***/typedef union {byte Byte;struct {byte DDRT0 :1; /* Data Direction Port T Bit 0 */byte DDRT1 :1; /* Data Direction Port T Bit 1 */byte DDRT2 :1; /* Data Direction Port T Bit 2 */byte DDRT3 :1; /* Data Direction Port T Bit 3 */byte DDRT4 :1; /* Data Direction Port T Bit 4 */byte DDRT5 :1; /* Data Direction Port T Bit 5 */byte DDRT6 :1; /* Data Direction Port T Bit 6 */byte DDRT7 :1; /* Data Direction Port T Bit 7 */} Bits;struct {byte grpDDRT :8;} MergedBits;} DDRTSTR;extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);#define DDRT _DDRT.Byte#define DDRT_DDRT0 _DDRT.Bits.DDRT0#define DDRT_DDRT1 _DDRT.Bits.DDRT1#define DDRT_DDRT2 _DDRT.Bits.DDRT2#define DDRT_DDRT3 _DDRT.Bits.DDRT3#define DDRT_DDRT4 _DDRT.Bits.DDRT4#define DDRT_DDRT5 _DDRT.Bits.DDRT5#define DDRT_DDRT6 _DDRT.Bits.DDRT6#define DDRT_DDRT7 _DDRT.Bits.DDRT7#define DDRT_DDRT _DDRT.MergedBits.grpDDRT/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/typedef union {byte Byte;struct {byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */} Bits;struct {byte grpRDRT :8;} MergedBits;} RDRTSTR;extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);#define RDRT _RDRT.Byte#define RDRT_RDRT0 _RDRT.Bits.RDRT0#define RDRT_RDRT1 _RDRT.Bits.RDRT1#define RDRT_RDRT2 _RDRT.Bits.RDRT2#define RDRT_RDRT3 _RDRT.Bits.RDRT3#define RDRT_RDRT4 _RDRT.Bits.RDRT4#define RDRT_RDRT5 _RDRT.Bits.RDRT5#define RDRT_RDRT6 _RDRT.Bits.RDRT6#define RDRT_RDRT7 _RDRT.Bits.RDRT7#define RDRT_RDRT _RDRT.MergedBits.grpRDRT/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/typedef union {byte Byte;struct {byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */} Bits;struct {byte grpPERT :8;} MergedBits;} PERTSTR;extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);#define PERT _PERT.Byte#define PERT_PERT0 _PERT.Bits.PERT0#define PERT_PERT1 _PERT.Bits.PERT1#define PERT_PERT2 _PERT.Bits.PERT2#define PERT_PERT3 _PERT.Bits.PERT3#define PERT_PERT4 _PERT.Bits.PERT4#define PERT_PERT5 _PERT.Bits.PERT5#define PERT_PERT6 _PERT.Bits.PERT6#define PERT_PERT7 _PERT.Bits.PERT7#define PERT_PERT _PERT.MergedBits.grpPERT/*** PPST - Port T Polarity Select Register; 0x00000245 ***/typedef union {byte Byte;struct {byte PPST0 :1; /* Pull Select Port T Bit 0 */byte PPST1 :1; /* Pull Select Port T Bit 1 */byte PPST2 :1; /* Pull Select Port T Bit 2 */byte PPST3 :1; /* Pull Select Port T Bit 3 */byte PPST4 :1; /* Pull Select Port T Bit 4 */byte PPST5 :1; /* Pull Select Port T Bit 5 */byte PPST6 :1; /* Pull Select Port T Bit 6 */byte PPST7 :1; /* Pull Select Port T Bit 7 */} Bits;struct {byte grpPPST :8;} MergedBits;} PPSTSTR;extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);#define PPST _PPST.Byte#define PPST_PPST0 _PPST.Bits.PPST0#define PPST_PPST1 _PPST.Bits.PPST1#define PPST_PPST2 _PPST.Bits.PPST2#define PPST_PPST3 _PPST.Bits.PPST3#define PPST_PPST4 _PPST.Bits.PPST4#define PPST_PPST5 _PPST.Bits.PPST5#define PPST_PPST6 _PPST.Bits.PPST6#define PPST_PPST7 _PPST.Bits.PPST7#define PPST_PPST _PPST.MergedBits.grpPPST/*** MODRR - Module Routing Register; 0x00000247 ***/typedef union {byte Byte;struct {byte MODRR0 :1; /* Module Routing Bit 0 */byte MODRR1 :1; /* Module Routing Bit 1 */byte MODRR2 :1; /* Module Routing Bit 2 */byte MODRR3 :1; /* Module Routing Bit 3 */byte MODRR4 :1; /* Module Routing Bit 4 */byte :1;byte :1;byte :1;} Bits;struct {byte grpMODRR :5;byte :1;byte :1;byte :1;} MergedBits;} MODRRSTR;extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000247);#define MODRR _MODRR.Byte#define MODRR_MODRR0 _MODRR.Bits.MODRR0#define MODRR_MODRR1 _MODRR.Bits.MODRR1#define MODRR_MODRR2 _MODRR.Bits.MODRR2#define MODRR_MODRR3 _MODRR.Bits.MODRR3#define MODRR_MODRR4 _MODRR.Bits.MODRR4#define MODRR_MODRR _MODRR.MergedBits.grpMODRR/*** PTS - Port S I/O Register; 0x00000248 ***/typedef union {byte Byte;struct {byte PTS0 :1; /* Port S Bit 0 */byte PTS1 :1; /* Port S Bit 1 */byte PTS2 :1; /* Port S Bit 2 */byte PTS3 :1; /* Port S Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpPTS :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} PTSSTR;extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);#define PTS _PTS.Byte#define PTS_PTS0 _PTS.Bits.PTS0#define PTS_PTS1 _PTS.Bits.PTS1#define PTS_PTS2 _PTS.Bits.PTS2#define PTS_PTS3 _PTS.Bits.PTS3#define PTS_PTS _PTS.MergedBits.grpPTS/*** PTIS - Port S Input; 0x00000249 ***/typedef union {byte Byte;struct {byte PTIS0 :1; /* Port S Bit 0 */byte PTIS1 :1; /* Port S Bit 1 */byte PTIS2 :1; /* Port S Bit 2 */byte PTIS3 :1; /* Port S Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpPTIS :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} PTISSTR;extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);#define PTIS _PTIS.Byte#define PTIS_PTIS0 _PTIS.Bits.PTIS0#define PTIS_PTIS1 _PTIS.Bits.PTIS1#define PTIS_PTIS2 _PTIS.Bits.PTIS2#define PTIS_PTIS3 _PTIS.Bits.PTIS3#define PTIS_PTIS _PTIS.MergedBits.grpPTIS/*** DDRS - Port S Data Direction Register; 0x0000024A ***/typedef union {byte Byte;struct {byte DDRS0 :1; /* Data Direction Port S Bit 0 */byte DDRS1 :1; /* Data Direction Port S Bit 1 */byte DDRS2 :1; /* Data Direction Port S Bit 2 */byte DDRS3 :1; /* Data Direction Port S Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpDDRS :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} DDRSSTR;extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);#define DDRS _DDRS.Byte#define DDRS_DDRS0 _DDRS.Bits.DDRS0#define DDRS_DDRS1 _DDRS.Bits.DDRS1#define DDRS_DDRS2 _DDRS.Bits.DDRS2#define DDRS_DDRS3 _DDRS.Bits.DDRS3#define DDRS_DDRS _DDRS.MergedBits.grpDDRS/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/typedef union {byte Byte;struct {byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpRDRS :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} RDRSSTR;extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);#define RDRS _RDRS.Byte#define RDRS_RDRS0 _RDRS.Bits.RDRS0#define RDRS_RDRS1 _RDRS.Bits.RDRS1#define RDRS_RDRS2 _RDRS.Bits.RDRS2#define RDRS_RDRS3 _RDRS.Bits.RDRS3#define RDRS_RDRS _RDRS.MergedBits.grpRDRS/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/typedef union {byte Byte;struct {byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpPERS :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} PERSSTR;extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);#define PERS _PERS.Byte#define PERS_PERS0 _PERS.Bits.PERS0#define PERS_PERS1 _PERS.Bits.PERS1#define PERS_PERS2 _PERS.Bits.PERS2#define PERS_PERS3 _PERS.Bits.PERS3#define PERS_PERS _PERS.MergedBits.grpPERS/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/typedef union {byte Byte;struct {byte PPSS0 :1; /* Pull Select Port S Bit 0 */byte PPSS1 :1; /* Pull Select Port S Bit 1 */byte PPSS2 :1; /* Pull Select Port S Bit 2 */byte PPSS3 :1; /* Pull Select Port S Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpPPSS :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} PPSSSTR;extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);#define PPSS _PPSS.Byte#define PPSS_PPSS0 _PPSS.Bits.PPSS0#define PPSS_PPSS1 _PPSS.Bits.PPSS1#define PPSS_PPSS2 _PPSS.Bits.PPSS2#define PPSS_PPSS3 _PPSS.Bits.PPSS3#define PPSS_PPSS _PPSS.MergedBits.grpPPSS/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/typedef union {byte Byte;struct {byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */byte :1;byte :1;byte :1;byte :1;} Bits;struct {byte grpWOMS :4;byte :1;byte :1;byte :1;byte :1;} MergedBits;} WOMSSTR;extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);#define WOMS _WOMS.Byte#define WOMS_WOMS0 _WOMS.Bits.WOMS0#define WOMS_WOMS1 _WOMS.Bits.WOMS1#define WOMS_WOMS2 _WOMS.Bits.WOMS2#define WOMS_WOMS3 _WOMS.Bits.WOMS3#define WOMS_WOMS _WOMS.MergedBits.grpWOMS/*** PTM - Port M I/O Register; 0x00000250 ***/typedef union {byte Byte;struct {byte PTM0 :1; /* Port T Bit 0 */byte PTM1 :1; /* Port T Bit 1 */byte PTM2 :1; /* Port T Bit 2 */byte PTM3 :1; /* Port T Bit 3 */byte PTM4 :1; /* Port T Bit 4 */byte PTM5 :1; /* Port T Bit 5 */byte :1;byte :1;} Bits;struct {byte grpPTM :6;byte :1;byte :1;} MergedBits;} PTMSTR;extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);#define PTM _PTM.Byte#define PTM_PTM0 _PTM.Bits.PTM0#define PTM_PTM1 _PTM.Bits.PTM1#define PTM_PTM2 _PTM.Bits.PTM2#define PTM_PTM3 _PTM.Bits.PTM3#define PTM_PTM4 _PTM.Bits.PTM4#define PTM_PTM5 _PTM.Bits.PTM5#define PTM_PTM _PTM.MergedBits.grpPTM/*** PTIM - Port M Input; 0x00000251 ***/typedef union {byte Byte;struct {byte PTIM0 :1; /* Port M Bit 0 */byte PTIM1 :1; /* Port M Bit 1 */byte PTIM2 :1; /* Port M Bit 2 */byte PTIM3 :1; /* Port M Bit 3 */byte PTIM4 :1; /* Port M Bit 4 */byte PTIM5 :1; /* Port M Bit 5 */byte :1;byte :1;} Bits;struct {byte grpPTIM :6;byte :1;byte :1;} MergedBits;} PTIMSTR;extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);#define PTIM _PTIM.Byte#define PTIM_PTIM0 _PTIM.Bits.PTIM0#define PTIM_PTIM1 _PTIM.Bits.PTIM1#define PTIM_PTIM2 _PTIM.Bits.PTIM2#define PTIM_PTIM3 _PTIM.Bits.PTIM3#define PTIM_PTIM4 _PTIM.Bits.PTIM4#define PTIM_PTIM5 _PTIM.Bits.PTIM5#define PTIM_PTIM _PTIM.MergedBits.grpPTIM/*** DDRM - Port M Data Direction Register; 0x00000252 ***/typedef union {byte Byte;struct {byte DDRM0 :1; /* Data Direction Port M Bit 0 */byte DDRM1 :1; /* Data Direction Port M Bit 1 */byte DDRM2 :1; /* Data Direction Port M Bit 2 */byte DDRM3 :1; /* Data Direction Port M Bit 3 */byte DDRM4 :1; /* Data Direction Port M Bit 4 */byte DDRM5 :1; /* Data Direction Port M Bit 5 */byte :1;byte :1;} Bits;struct {byte grpDDRM :6;byte :1;byte :1;} MergedBits;} DDRMSTR;extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);#define DDRM _DDRM.Byte#define DDRM_DDRM0 _DDRM.Bits.DDRM0#define DDRM_DDRM1 _DDRM.Bits.DDRM1#define DDRM_DDRM2 _DDRM.Bits.DDRM2#define DDRM_DDRM3 _DDRM.Bits.DDRM3#define DDRM_DDRM4 _DDRM.Bits.DDRM4#define DDRM_DDRM5 _DDRM.Bits.DDRM5#define DDRM_DDRM _DDRM.MergedBits.grpDDRM/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/typedef union {byte Byte;struct {byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */byte :1;byte :1;} Bits;struct {byte grpRDRM :6;byte :1;byte :1;} MergedBits;} RDRMSTR;extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);#define RDRM _RDRM.Byte#define RDRM_RDRM0 _RDRM.Bits.RDRM0#define RDRM_RDRM1 _RDRM.Bits.RDRM1#define RDRM_RDRM2 _RDRM.Bits.RDRM2#define RDRM_RDRM3 _RDRM.Bits.RDRM3#define RDRM_RDRM4 _RDRM.Bits.RDRM4#define RDRM_RDRM5 _RDRM.Bits.RDRM5#define RDRM_RDRM _RDRM.MergedBits.grpRDRM/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/typedef union {byte Byte;struct {byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */byte :1;byte :1;} Bits;struct {byte grpPERM :6;byte :1;byte :1;} MergedBits;} PERMSTR;extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);#define PERM _PERM.Byte#define PERM_PERM0 _PERM.Bits.PERM0#define PERM_PERM1 _PERM.Bits.PERM1#define PERM_PERM2 _PERM.Bits.PERM2#define PERM_PERM3 _PERM.Bits.PERM3#define PERM_PERM4 _PERM.Bits.PERM4#define PERM_PERM5 _PERM.Bits.PERM5#define PERM_PERM _PERM.MergedBits.grpPERM/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/typedef union {byte Byte;struct {byte PPSM0 :1; /* Pull Select Port M Bit 0 */byte PPSM1 :1; /* Pull Select Port M Bit 1 */byte PPSM2 :1; /* Pull Select Port M Bit 2 */byte PPSM3 :1; /* Pull Select Port M Bit 3 */byte PPSM4 :1; /* Pull Select Port M Bit 4 */byte PPSM5 :1; /* Pull Select Port M Bit 5 */byte :1;byte :1;} Bits;struct {byte grpPPSM :6;byte :1;byte :1;} MergedBits;} PPSMSTR;extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);#define PPSM _PPSM.Byte#define PPSM_PPSM0 _PPSM.Bits.PPSM0#define PPSM_PPSM1 _PPSM.Bits.PPSM1#define PPSM_PPSM2 _PPSM.Bits.PPSM2#define PPSM_PPSM3 _PPSM.Bits.PPSM3#define PPSM_PPSM4 _PPSM.Bits.PPSM4#define PPSM_PPSM5 _PPSM.Bits.PPSM5#define PPSM_PPSM _PPSM.MergedBits.grpPPSM/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/typedef union {byte Byte;struct {byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */byte :1;byte :1;} Bits;struct {byte grpWOMM :6;byte :1;byte :1;} MergedBits;} WOMMSTR;extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);#define WOMM _WOMM.Byte#define WOMM_WOMM0 _WOMM.Bits.WOMM0#define WOMM_WOMM1 _WOMM.Bits.WOMM1#define WOMM_WOMM2 _WOMM.Bits.WOMM2#define WOMM_WOMM3 _WOMM.Bits.WOMM3#define WOMM_WOMM4 _WOMM.Bits.WOMM4#define WOMM_WOMM5 _WOMM.Bits.WOMM5#define WOMM_WOMM _WOMM.MergedBits.grpWOMM/*** PTP - Port P I/O Register; 0x00000258 ***/typedef union {byte Byte;struct {byte PTP0 :1; /* Port P Bit 0 */byte PTP1 :1; /* Port P Bit 1 */byte PTP2 :1; /* Port P Bit 2 */byte PTP3 :1; /* Port P Bit 3 */byte PTP4 :1; /* Port P Bit 4 */byte PTP5 :1; /* Port P Bit 5 */byte PTP6 :1; /* Port P Bit 6 */byte PTP7 :1; /* Port P Bit 7 */} Bits;struct {byte grpPTP :8;} MergedBits;} PTPSTR;extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);#define PTP _PTP.Byte#define PTP_PTP0 _PTP.Bits.PTP0#define PTP_PTP1 _PTP.Bits.PTP1#define PTP_PTP2 _PTP.Bits.PTP2#define PTP_PTP3 _PTP.Bits.PTP3#define PTP_PTP4 _PTP.Bits.PTP4#define PTP_PTP5 _PTP.Bits.PTP5#define PTP_PTP6 _PTP.Bits.PTP6#define PTP_PTP7 _PTP.Bits.PTP7#define PTP_PTP _PTP.MergedBits.grpPTP/*** PTIP - Port P Input; 0x00000259 ***/typedef union {byte Byte;struct {byte PTIP0 :1; /* Port P Bit 0 */byte PTIP1 :1; /* Port P Bit 1 */byte PTIP2 :1; /* Port P Bit 2 */byte PTIP3 :1; /* Port P Bit 3 */byte PTIP4 :1; /* Port P Bit 4 */byte PTIP5 :1; /* Port P Bit 5 */byte PTIP6 :1; /* Port P Bit 6 */byte PTIP7 :1; /* Port P Bit 7 */} Bits;struct {byte grpPTIP :8;} MergedBits;} PTIPSTR;extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);#define PTIP _PTIP.Byte#define PTIP_PTIP0 _PTIP.Bits.PTIP0#define PTIP_PTIP1 _PTIP.Bits.PTIP1#define PTIP_PTIP2 _PTIP.Bits.PTIP2#define PTIP_PTIP3 _PTIP.Bits.PTIP3#define PTIP_PTIP4 _PTIP.Bits.PTIP4#define PTIP_PTIP5 _PTIP.Bits.PTIP5#define PTIP_PTIP6 _PTIP.Bits.PTIP6#define PTIP_PTIP7 _PTIP.Bits.PTIP7#define PTIP_PTIP _PTIP.MergedBits.grpPTIP/*** DDRP - Port P Data Direction Register; 0x0000025A ***/typedef union {byte Byte;struct {byte DDRP0 :1; /* Data Direction Port P Bit 0 */byte DDRP1 :1; /* Data Direction Port P Bit 1 */byte DDRP2 :1; /* Data Direction Port P Bit 2 */byte DDRP3 :1; /* Data Direction Port P Bit 3 */byte DDRP4 :1; /* Data Direction Port P Bit 4 */byte DDRP5 :1; /* Data Direction Port P Bit 5 */byte DDRP6 :1; /* Data Direction Port P Bit 6 */byte DDRP7 :1; /* Data Direction Port P Bit 7 */} Bits;struct {byte grpDDRP :8;} MergedBits;} DDRPSTR;extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);#define DDRP _DDRP.Byte#define DDRP_DDRP0 _DDRP.Bits.DDRP0#define DDRP_DDRP1 _DDRP.Bits.DDRP1#define DDRP_DDRP2 _DDRP.Bits.DDRP2#define DDRP_DDRP3 _DDRP.Bits.DDRP3#define DDRP_DDRP4 _DDRP.Bits.DDRP4#define DDRP_DDRP5 _DDRP.Bits.DDRP5#define DDRP_DDRP6 _DDRP.Bits.DDRP6#define DDRP_DDRP7 _DDRP.Bits.DDRP7#define DDRP_DDRP _DDRP.MergedBits.grpDDRP/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/typedef union {byte Byte;struct {byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */} Bits;struct {byte grpRDRP :8;} MergedBits;} RDRPSTR;extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);#define RDRP _RDRP.Byte#define RDRP_RDRP0 _RDRP.Bits.RDRP0#define RDRP_RDRP1 _RDRP.Bits.RDRP1#define RDRP_RDRP2 _RDRP.Bits.RDRP2#define RDRP_RDRP3 _RDRP.Bits.RDRP3#define RDRP_RDRP4 _RDRP.Bits.RDRP4#define RDRP_RDRP5 _RDRP.Bits.RDRP5#define RDRP_RDRP6 _RDRP.Bits.RDRP6#define RDRP_RDRP7 _RDRP.Bits.RDRP7#define RDRP_RDRP _RDRP.MergedBits.grpRDRP/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/typedef union {byte Byte;struct {byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */} Bits;struct {byte grpPERP :8;} MergedBits;} PERPSTR;extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);#define PERP _PERP.Byte#define PERP_PERP0 _PERP.Bits.PERP0#define PERP_PERP1 _PERP.Bits.PERP1#define PERP_PERP2 _PERP.Bits.PERP2#define PERP_PERP3 _PERP.Bits.PERP3#define PERP_PERP4 _PERP.Bits.PERP4#define PERP_PERP5 _PERP.Bits.PERP5#define PERP_PERP6 _PERP.Bits.PERP6#define PERP_PERP7 _PERP.Bits.PERP7#define PERP_PERP _PERP.MergedBits.grpPERP/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/typedef union {byte Byte;struct {byte PPSP0 :1; /* Pull Select Port P Bit 0 */byte PPSP1 :1; /* Pull Select Port P Bit 1 */byte PPSP2 :1; /* Pull Select Port P Bit 2 */byte PPSP3 :1; /* Pull Select Port P Bit 3 */byte PPSP4 :1; /* Pull Select Port P Bit 4 */byte PPSP5 :1; /* Pull Select Port P Bit 5 */byte PPSP6 :1; /* Pull Select Port P Bit 6 */byte PPSP7 :1; /* Pull Select Port P Bit 7 */} Bits;struct {byte grpPPSP :8;} MergedBits;} PPSPSTR;extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);#define PPSP _PPSP.Byte#define PPSP_PPSP0 _PPSP.Bits.PPSP0#define PPSP_PPSP1 _PPSP.Bits.PPSP1#define PPSP_PPSP2 _PPSP.Bits.PPSP2#define PPSP_PPSP3 _PPSP.Bits.PPSP3#define PPSP_PPSP4 _PPSP.Bits.PPSP4#define PPSP_PPSP5 _PPSP.Bits.PPSP5#define PPSP_PPSP6 _PPSP.Bits.PPSP6#define PPSP_PPSP7 _PPSP.Bits.PPSP7#define PPSP_PPSP _PPSP.MergedBits.grpPPSP/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/typedef union {byte Byte;struct {byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */} Bits;struct {byte grpPIEP :8;} MergedBits;} PIEPSTR;extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);#define PIEP _PIEP.Byte#define PIEP_PIEP0 _PIEP.Bits.PIEP0#define PIEP_PIEP1 _PIEP.Bits.PIEP1#define PIEP_PIEP2 _PIEP.Bits.PIEP2#define PIEP_PIEP3 _PIEP.Bits.PIEP3#define PIEP_PIEP4 _PIEP.Bits.PIEP4#define PIEP_PIEP5 _PIEP.Bits.PIEP5#define PIEP_PIEP6 _PIEP.Bits.PIEP6#define PIEP_PIEP7 _PIEP.Bits.PIEP7#define PIEP_PIEP _PIEP.MergedBits.grpPIEP/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/typedef union {byte Byte;struct {byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */} Bits;struct {byte grpPIFP :8;} MergedBits;} PIFPSTR;extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);#define PIFP _PIFP.Byte#define PIFP_PIFP0 _PIFP.Bits.PIFP0#define PIFP_PIFP1 _PIFP.Bits.PIFP1#define PIFP_PIFP2 _PIFP.Bits.PIFP2#define PIFP_PIFP3 _PIFP.Bits.PIFP3#define PIFP_PIFP4 _PIFP.Bits.PIFP4#define PIFP_PIFP5 _PIFP.Bits.PIFP5#define PIFP_PIFP6 _PIFP.Bits.PIFP6#define PIFP_PIFP7 _PIFP.Bits.PIFP7#define PIFP_PIFP _PIFP.MergedBits.grpPIFP/*** PTJ - Port J I/O Register; 0x00000268 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte PTJ6 :1; /* Port J Bit 6 */byte PTJ7 :1; /* Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpPTJ_6 :2;} MergedBits;} PTJSTR;extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);#define PTJ _PTJ.Byte#define PTJ_PTJ6 _PTJ.Bits.PTJ6#define PTJ_PTJ7 _PTJ.Bits.PTJ7#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6/*** PTIJ - Port J Input Register; 0x00000269 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte PTIJ6 :1; /* Port J Bit 6 */byte PTIJ7 :1; /* Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpPTIJ_6 :2;} MergedBits;} PTIJSTR;extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);#define PTIJ _PTIJ.Byte#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte DDRJ6 :1; /* Data Direction Port J Bit 6 */byte DDRJ7 :1; /* Data Direction Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpDDRJ_6 :2;} MergedBits;} DDRJSTR;extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);#define DDRJ _DDRJ.Byte#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpRDRJ_6 :2;} MergedBits;} RDRJSTR;extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);#define RDRJ _RDRJ.Byte#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpPERJ_6 :2;} MergedBits;} PERJSTR;extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);#define PERJ _PERJ.Byte#define PERJ_PERJ6 _PERJ.Bits.PERJ6#define PERJ_PERJ7 _PERJ.Bits.PERJ7#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte PPSJ6 :1; /* Pull Select Port J Bit 6 */byte PPSJ7 :1; /* Pull Select Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpPPSJ_6 :2;} MergedBits;} PPSJSTR;extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);#define PPSJ _PPSJ.Byte#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpPIEJ_6 :2;} MergedBits;} PIEJSTR;extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);#define PIEJ _PIEJ.Byte#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */} Bits;struct {byte :1;byte :1;byte :1;byte :1;byte :1;byte :1;byte grpPIFJ_6 :2;} MergedBits;} PIFJSTR;extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);#define PIFJ _PIFJ.Byte#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6/*** PTAD - Port AD I/O Register; 0x00000270 ***/typedef union {byte Byte;struct {byte PTAD0 :1; /* Port AD Bit 0 */byte PTAD1 :1; /* Port AD Bit 1 */byte PTAD2 :1; /* Port AD Bit 2 */byte PTAD3 :1; /* Port AD Bit 3 */byte PTAD4 :1; /* Port AD Bit 4 */byte PTAD5 :1; /* Port AD Bit 5 */byte PTAD6 :1; /* Port AD Bit 6 */byte PTAD7 :1; /* Port AD Bit 7 */} Bits;struct {byte grpPTAD :8;} MergedBits;} PTADSTR;extern volatile PTADSTR _PTAD @(REG_BASE + 0x00000270);#define PTAD _PTAD.Byte#define PTAD_PTAD0 _PTAD.Bits.PTAD0#define PTAD_PTAD1 _PTAD.Bits.PTAD1#define PTAD_PTAD2 _PTAD.Bits.PTAD2#define PTAD_PTAD3 _PTAD.Bits.PTAD3#define PTAD_PTAD4 _PTAD.Bits.PTAD4#define PTAD_PTAD5 _PTAD.Bits.PTAD5#define PTAD_PTAD6 _PTAD.Bits.PTAD6#define PTAD_PTAD7 _PTAD.Bits.PTAD7#define PTAD_PTAD _PTAD.MergedBits.grpPTAD/*** PTIAD - Port AD Input Register; 0x00000271 ***/typedef union {byte Byte;struct {byte PTIAD0 :1; /* Port AD Bit 0 */byte PTIAD1 :1; /* Port AD Bit 1 */byte PTIAD2 :1; /* Port AD Bit 2 */byte PTIAD3 :1; /* Port AD Bit 3 */byte PTIAD4 :1; /* Port AD Bit 4 */byte PTIAD5 :1; /* Port AD Bit 5 */byte PTIAD6 :1; /* Port AD Bit 6 */byte PTIAD7 :1; /* Port AD Bit 7 */} Bits;struct {byte grpPTIAD :8;} MergedBits;} PTIADSTR;extern volatile PTIADSTR _PTIAD @(REG_BASE + 0x00000271);#define PTIAD _PTIAD.Byte#define PTIAD_PTIAD0 _PTIAD.Bits.PTIAD0#define PTIAD_PTIAD1 _PTIAD.Bits.PTIAD1#define PTIAD_PTIAD2 _PTIAD.Bits.PTIAD2#define PTIAD_PTIAD3 _PTIAD.Bits.PTIAD3#define PTIAD_PTIAD4 _PTIAD.Bits.PTIAD4#define PTIAD_PTIAD5 _PTIAD.Bits.PTIAD5#define PTIAD_PTIAD6 _PTIAD.Bits.PTIAD6#define PTIAD_PTIAD7 _PTIAD.Bits.PTIAD7#define PTIAD_PTIAD _PTIAD.MergedBits.grpPTIAD/*** DDRAD - Port AD Data Direction Register; 0x00000272 ***/typedef union {byte Byte;struct {byte DDRAD0 :1; /* Port AD Data Direction Bit 0 */byte DDRAD1 :1; /* Port AD Data Direction Bit 1 */byte DDRAD2 :1; /* Port AD Data Direction Bit 2 */byte DDRAD3 :1; /* Port AD Data Direction Bit 3 */byte DDRAD4 :1; /* Port AD Data Direction Bit 4 */byte DDRAD5 :1; /* Port AD Data Direction Bit 5 */byte DDRAD6 :1; /* Port AD Data Direction Bit 6 */byte DDRAD7 :1; /* Port AD Data Direction Bit 7 */} Bits;struct {byte grpDDRAD :8;} MergedBits;} DDRADSTR;extern volatile DDRADSTR _DDRAD @(REG_BASE + 0x00000272);#define DDRAD _DDRAD.Byte#define DDRAD_DDRAD0 _DDRAD.Bits.DDRAD0#define DDRAD_DDRAD1 _DDRAD.Bits.DDRAD1#define DDRAD_DDRAD2 _DDRAD.Bits.DDRAD2#define DDRAD_DDRAD3 _DDRAD.Bits.DDRAD3#define DDRAD_DDRAD4 _DDRAD.Bits.DDRAD4#define DDRAD_DDRAD5 _DDRAD.Bits.DDRAD5#define DDRAD_DDRAD6 _DDRAD.Bits.DDRAD6#define DDRAD_DDRAD7 _DDRAD.Bits.DDRAD7#define DDRAD_DDRAD _DDRAD.MergedBits.grpDDRAD/*** RDRAD - Port AD Reduced Drive Register; 0x00000273 ***/typedef union {byte Byte;struct {byte RDRAD0 :1; /* Port AD Reduced Drive Bit 0 */byte RDRAD1 :1; /* Port AD Reduced Drive Bit 1 */byte RDRAD2 :1; /* Port AD Reduced Drive Bit 2 */byte RDRAD3 :1; /* Port AD Reduced Drive Bit 3 */byte RDRAD4 :1; /* Port AD Reduced Drive Bit 4 */byte RDRAD5 :1; /* Port AD Reduced Drive Bit 5 */byte RDRAD6 :1; /* Port AD Reduced Drive Bit 6 */byte RDRAD7 :1; /* Port AD Reduced Drive Bit 7 */} Bits;struct {byte grpRDRAD :8;} MergedBits;} RDRADSTR;extern volatile RDRADSTR _RDRAD @(REG_BASE + 0x00000273);#define RDRAD _RDRAD.Byte#define RDRAD_RDRAD0 _RDRAD.Bits.RDRAD0#define RDRAD_RDRAD1 _RDRAD.Bits.RDRAD1#define RDRAD_RDRAD2 _RDRAD.Bits.RDRAD2#define RDRAD_RDRAD3 _RDRAD.Bits.RDRAD3#define RDRAD_RDRAD4 _RDRAD.Bits.RDRAD4#define RDRAD_RDRAD5 _RDRAD.Bits.RDRAD5#define RDRAD_RDRAD6 _RDRAD.Bits.RDRAD6#define RDRAD_RDRAD7 _RDRAD.Bits.RDRAD7#define RDRAD_RDRAD _RDRAD.MergedBits.grpRDRAD/*** PERAD - Port AD Pull Device Enable Register; 0x00000274 ***/typedef union {byte Byte;struct {byte PERAD0 :1; /* Port AD Pull Device Enable Bit 0 */byte PERAD1 :1; /* Port AD Pull Device Enable Bit 1 */byte PERAD2 :1; /* Port AD Pull Device Enable Bit 2 */byte PERAD3 :1; /* Port AD Pull Device Enable Bit 3 */byte PERAD4 :1; /* Port AD Pull Device Enable Bit 4 */byte PERAD5 :1; /* Port AD Pull Device Enable Bit 5 */byte PERAD6 :1; /* Port AD Pull Device Enable Bit 6 */byte PERAD7 :1; /* Port AD Pull Device Enable Bit 7 */} Bits;struct {byte grpPERAD :8;} MergedBits;} PERADSTR;extern volatile PERADSTR _PERAD @(REG_BASE + 0x00000274);#define PERAD _PERAD.Byte#define PERAD_PERAD0 _PERAD.Bits.PERAD0#define PERAD_PERAD1 _PERAD.Bits.PERAD1#define PERAD_PERAD2 _PERAD.Bits.PERAD2#define PERAD_PERAD3 _PERAD.Bits.PERAD3#define PERAD_PERAD4 _PERAD.Bits.PERAD4#define PERAD_PERAD5 _PERAD.Bits.PERAD5#define PERAD_PERAD6 _PERAD.Bits.PERAD6#define PERAD_PERAD7 _PERAD.Bits.PERAD7#define PERAD_PERAD _PERAD.MergedBits.grpPERAD/*** PPSAD - Port AD Polarity Select Register; 0x00000275 ***/typedef union {byte Byte;struct {byte PPSAD0 :1; /* Port AD Polarity Select Bit 0 */byte PPSAD1 :1; /* Port AD Polarity Select Bit 1 */byte PPSAD2 :1; /* Port AD Polarity Select Bit 2 */byte PPSAD3 :1; /* Port AD Polarity Select Bit 3 */byte PPSAD4 :1; /* Port AD Polarity Select Bit 4 */byte PPSAD5 :1; /* Port AD Polarity Select Bit 5 */byte PPSAD6 :1; /* Port AD Polarity Select Bit 6 */byte PPSAD7 :1; /* Port AD Polarity Select Bit 7 */} Bits;struct {byte grpPPSAD :8;} MergedBits;} PPSADSTR;extern volatile PPSADSTR _PPSAD @(REG_BASE + 0x00000275);#define PPSAD _PPSAD.Byte#define PPSAD_PPSAD0 _PPSAD.Bits.PPSAD0#define PPSAD_PPSAD1 _PPSAD.Bits.PPSAD1#define PPSAD_PPSAD2 _PPSAD.Bits.PPSAD2#define PPSAD_PPSAD3 _PPSAD.Bits.PPSAD3#define PPSAD_PPSAD4 _PPSAD.Bits.PPSAD4#define PPSAD_PPSAD5 _PPSAD.Bits.PPSAD5#define PPSAD_PPSAD6 _PPSAD.Bits.PPSAD6#define PPSAD_PPSAD7 _PPSAD.Bits.PPSAD7#define PPSAD_PPSAD _PPSAD.MergedBits.grpPPSAD/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/typedef union {byte Byte;struct {byte :1;byte UNSEC :1; /* Unsecure */byte CLKSW :1; /* Clock switch */byte TRACE :1; /* TRACE1 BDM firmware command is being executed */byte SDV :1; /* Shift data valid */byte ENTAG :1; /* Tagging enable */byte BDMACT :1; /* BDM active status */byte ENBDM :1; /* Enable BDM */} Bits;} BDMSTSSTR;extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);#define BDMSTS _BDMSTS.Byte#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW#define BDMSTS_TRACE _BDMSTS.Bits.TRACE#define BDMSTS_SDV _BDMSTS.Bits.SDV#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/typedef union {byte Byte;struct {byte CCR0 :1; /* BDM CCR Holding Bit 0 */byte CCR1 :1; /* BDM CCR Holding Bit 1 */byte CCR2 :1; /* BDM CCR Holding Bit 2 */byte CCR3 :1; /* BDM CCR Holding Bit 3 */byte CCR4 :1; /* BDM CCR Holding Bit 4 */byte CCR5 :1; /* BDM CCR Holding Bit 5 */byte CCR6 :1; /* BDM CCR Holding Bit 6 */byte CCR7 :1; /* BDM CCR Holding Bit 7 */} Bits;struct {byte grpCCR :8;} MergedBits;} BDMCCRSTR;extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);#define BDMCCR _BDMCCR.Byte#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/typedef union {byte Byte;struct {byte :1;byte :1;byte :1;byte REG11 :1; /* Internal register map position */byte REG12 :1; /* Internal register map position */byte REG13 :1; /* Internal register map position */byte REG14 :1; /* Internal register map position */byte REG15 :1; /* Internal register map position */} Bits;struct {byte :1;byte :1;byte :1;byte grpREG_11 :5;} MergedBits;} BDMINRSTR;extern volatile BDMINRSTR _BDMINR @(0x0000FF07);#define BDMINR _BDMINR.Byte#define BDMINR_REG11 _BDMINR.Bits.REG11#define BDMINR_REG12 _BDMINR.Bits.REG12#define BDMINR_REG13 _BDMINR.Bits.REG13#define BDMINR_REG14 _BDMINR.Bits.REG14#define BDMINR_REG15 _BDMINR.Bits.REG15#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11#define BDMINR_REG BDMINR_REG_11/* Watchdog reset macro */#ifdef _lint#define __RESET_WATCHDOG() /* empty */#else#define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */#endif#endif/*** ###################################################################**** This file was created by UNIS Processor Expert 03.33 for** the Motorola HCS12 series of microcontrollers.**** ###################################################################*/
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