URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB91460_Softune/] [PRC/] [set_SIMULATE.prc] - Rev 867
Go to most recent revision | Compare with Previous | Blame | View Log
# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
# ELIGIBILITY FOR ANY PURPOSES. */
# (C) Fujitsu Microelectronics Europe GmbH */
# Environment and memory manioulation after program upload
print "patch reset vector to \"__start\"\n";
SET MEMORY/WORD 0xFFFFC=__start
Go to most recent revision | Compare with Previous | Blame | View Log