URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [board.h] - Rev 800
Compare with Previous | Blame | View Log
#ifndef _BOARD_H_ #define _BOARD_H_ #define SYS_CLK 25000000 #define IN_CLK 25000000 //#define UART_NUM_CORES 2 #undef UART_NUM_CORES #define UART0_BAUD_RATE 115200 #define UART0_BASE 0x90000000 #define UART0_IRQ 2 //#define GPIO_NUM_CORES 2 #undef GPIO_NUM_CORES #define GPIO0_BASE 0x91000000 #define GPIO0_IRQ 3 #define DMA_BASE 0x9a000000 #define DMA_IRQ 11 #endif