OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [support.c] - Rev 584

Go to most recent revision | Compare with Previous | Blame | View Log

/* Support */
#include "spr_defs.h"
#include "support.h"
#include "int.h"
 
void int_main();
 
void ext_except(void) {
	int_main();
}
 
/* Start function, called by reset exception handler.  */
static char *main_argv[2] = {"NULL", " "};
 
void _main(void) {
	int i = main(2, main_argv);
	or32_exit (i);  
}
 
/* return value by making a syscall */
void or32_exit(int i) {
	asm("l.add r3,r0,%0": : "r" (i));
	asm("l.nop %0": :"K" (NOP_EXIT));
	while (1);
}
 
 
/* print long */
void report(unsigned long value) {
	asm("l.addi\tr3,%0,0": :"r" (value));
	asm("l.nop %0": :"K" (NOP_REPORT));
}
 
/* For writing into SPR. */
void mtspr(unsigned long spr, unsigned long value) {	
	asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
}
 
/* For reading SPR. */
unsigned long mfspr(unsigned long spr) {	
	unsigned long value;
	asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
	return value;
}
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.