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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_SP_FPU_Xilinx_Virtex5_GCC/] [__xps/] [ise/] [system.xise] - Rev 594
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files/>
<properties>
<property xil_pn:name="Device" xil_pn:value="xa2c*"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive CoolRunner2"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="system"/>
<property xil_pn:name="PROP_Enable_Incremental_Messaging" xil_pn:value="true"/>
<property xil_pn:name="PROP_Enable_Message_Filtering" xil_pn:value="true"/>
<property xil_pn:name="Package" xil_pn:value="*"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-*"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>
<bindings/>
<libraries/>
<partitions>
<partition xil_pn:name="/"/>
</partitions>
</project>
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