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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [dbsct.c] - Rev 612
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/***********************************************************************/ /* */ /* FILE :dbsct.c */ /* DATE :Sun, Dec 27, 2009 */ /* DESCRIPTION :Setting of B,R Section */ /* CPU TYPE :Other */ /* */ /* This file is generated by Renesas Project Generator (Ver.4.16). */ /* */ /***********************************************************************/ #include "typedefine.h" #pragma section $DSEC static const struct { _UBYTE *rom_s; /* Start address of the initialized data section in ROM */ _UBYTE *rom_e; /* End address of the initialized data section in ROM */ _UBYTE *ram_s; /* Start address of the initialized data section in RAM */ } DTBL[] = { { __sectop("D"), __secend("D"), __sectop("R") } }; #pragma section $BSEC static const struct { _UBYTE *b_s; /* Start address of non-initialized data section */ _UBYTE *b_e; /* End address of non-initialized data section */ } BTBL[] = { { __sectop("B"), __secend("B") } };
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