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https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [msp430_IAR/] [settings/] [RTOSDemo.dni] - Rev 613
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[Interrupts]
Enabled=1
[MemoryMap]
Enabled=0
Base=0
UseAuto=0
TypeViolation=1
UnspecRange=1
ActionState=1
[TraceHelper]
Enabled=0
ShowSource=1
[State Storage]
Control Register=0
[Sequencer]
Control Register=0
NextState0=0
NextState1=0
[Action Register]
Break=3
State Storage=0
[DisAssemblyWindow]
NumStates=_ 1
State 1=_ 1
[Profiling]
Enabled=0
[StackPlugin]
Enabled=1
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnHow=0
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[Breakpoints]
Count=0
[FET]
Clock mode=14
Extended Clock mode=61663
Extended Clock Control Enable=0
Advanced Extended Clock Control=0
Emulation mode=0
Free running=0
Shutting Down=3
[Memory Dump]
Start address=
Lenghth=
Address info=0
Format=0
Dump registers=0
PC=0
SP=0
SR=0
all registers=0
File name=
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