URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [powerpc/] [new_exception_processing/] [c_isr.inl] - Rev 773
Go to most recent revision | Compare with Previous | Blame | View Log
RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
{
register unsigned int isr_nesting_level;
/*
* Move from special purpose register 0 (mfspr SPRG0, r3)
*/
asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level));
return isr_nesting_level;
}
Go to most recent revision | Compare with Previous | Blame | View Log