OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [helas403/] [README] - Rev 30

Go to most recent revision | Compare with Previous | Blame | View Log

#
#  $Id: README,v 1.2 2001-09-27 12:00:36 chris Exp $
#

BSP NAME:           helas403
BOARD:              IMD, helas-ppc
BUS:                N/A
CPU FAMILY:         ppc
CPU:                PowerPC 403GA
COPROCESSORS:       N/A
MODE:               32 bit mode

DEBUG MONITOR:      Modified Motorola FBUG

PERIPHERALS
===========
TIMERS:             403GA internal
  RESOLUTION:         .04 microseconds
SERIAL PORTS:       403GA internal 
REAL-TIME CLOCK:    403GA internal
DMA:                403GA internal
VIDEO:              none
SCSI:               none
NETWORKING:         none

DRIVER INFORMATION
==================
CLOCK DRIVER:       403GA internal
IOSUPP DRIVER:      N/A
SHMSUPP:            N/A
TIMER DRIVER:       403GA internal
TTY DRIVER:         403GA internal

STDIO
=====
PORT:               Console port 0
ELECTRICAL:         RS-232
BAUD:               9600
BITS PER CHARACTER: 8
PARITY:             None
STOP BITS:          1

Notes
=====

Board description
-----------------
clock rate:     25 MHz
bus width:      8-bit PROM, 32-bit DRAM
ROM:            Up to 512KByte (Am29F040), 90 nsec chip select 0
RAM:            4 to 32 MByte DRAM SIMM (autodetect), 70 nsec,
                no parity, at CS7 or CS6+CS7 (for two-bank-SIMMs)


helas403 only supports single processor operations.

Porting
-------
This board support package is written for a typical PPC403GA
system. The rough features of this board are described above.

This BSP contains files for two startup methods:
- Direct start from Flash after powerup (with code run out of flash):
  This is the default configuration, it uses the files
        flashentry/flashentry.s
        startup/linkcmds

 Please note, that this configuration is good to startup the system,
but it will not gain maximum performance due to slow Flash access (8
bit wide only)

- Start after software download into DRAM:
  This configuration will use:
        dlentry/dlentry.s
        startup/linkcmds.dl

If you want to use the download configuration, it is sufficient to
rename the file "startup/linkcmds.dl" to "startup/linkcmds", it will
automatically reference the dlentry.s as entry code. (Renaming is not
quite elegant, a more sophisticated solution will follow in future,
any hints welcome ;-)

For adapting this BSP to other boards, the following files should be
modified:

- c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s
        for the memory controller configuration and other basic stuff

- c/src/lib/libbsp/powerpc/helas403/startup/linkcmds[.dl]
        for the memory layout required

- c/src/lib/libbsp/powerpc/helas403/startup/bspstart.c
        for adaption of BSP_Configuration. here you can select
        the clock source for the timers and the serial interface
        (system clock or external clock pin), the clock rates, initial
        baud rate and other stuff

- c/src/lib/libbsp/powerpc/helas403/include/bsp.h
        some BSP-related constants

The actual drivers are placed in 
- c/src/lib/libcpu/powerpc/ppc403/*
        well, they should be generic, so there _should_ be no reason
        to mess around there (but who knows...)


Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.