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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [powerpc/] [shared/] [io.h] - Rev 30
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/* * io.h * * This file contains inline implementation of function to * deal with IO. * * It is a stripped down version of linux ppc file... * * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) * Canon Centre Recherche France. * * The license and distribution terms for this file may be * found in found in the file LICENSE in this distribution or at * http://www.OARcorp.com/rtems/license.html. * * $Id: io.h,v 1.2 2001-09-27 12:01:30 chris Exp $ */ #ifndef _LIBCPU_IO_H_ #define _LIBCPU_IO_H_ #define PREP_ISA_IO_BASE 0x80000000 #define PREP_ISA_MEM_BASE 0xc0000000 #define PREP_PCI_DRAM_OFFSET 0x80000000 #define _IO_BASE PREP_ISA_IO_BASE #define _ISA_MEM_BASE PREP_ISA_MEM_BASE #define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET #ifndef ASM #define inb(port) in_8((unsigned char *)((port)+_IO_BASE)) #define outb(val, port) out_8((unsigned char *)((port)+_IO_BASE), (val)) #define inw(port) in_le16((unsigned short *)((port)+_IO_BASE)) #define outw(val, port) out_le16((unsigned short *)((port)+_IO_BASE), (val)) #define inl(port) in_le32((unsigned *)((port)+_IO_BASE)) #define outl(val, port) out_le32((unsigned *)((port)+_IO_BASE), (val)) /* * Enforce In-order Execution of I/O: * Acts as a barrier to ensure all previous I/O accesses have * completed before any further ones are issued. */ extern inline void eieio(void) { __asm__ __volatile__ ("eieio"); } /* Enforce in-order execution of data I/O. * No distinction between read/write on PPC; use eieio for all three. */ #define iobarrier_rw() eieio() #define iobarrier_r() eieio() #define iobarrier_w() eieio() /* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. */ extern inline int in_8(volatile unsigned char *addr) { int ret; __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); return ret; } extern inline void out_8(volatile unsigned char *addr, int val) { __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } extern inline int in_le16(volatile unsigned short *addr) { int ret; __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : "r" (addr), "m" (*addr)); return ret; } extern inline int in_be16(volatile unsigned short *addr) { int ret; __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); return ret; } extern inline void out_le16(volatile unsigned short *addr, int val) { __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : "r" (val), "r" (addr)); } extern inline void out_be16(volatile unsigned short *addr, int val) { __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } extern inline unsigned in_le32(volatile unsigned *addr) { unsigned ret; __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : "r" (addr), "m" (*addr)); return ret; } extern inline unsigned in_be32(volatile unsigned *addr) { unsigned ret; __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); return ret; } extern inline void out_le32(volatile unsigned *addr, int val) { __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : "r" (val), "r" (addr)); } extern inline void out_be32(volatile unsigned *addr, int val) { __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } #endif /* ASM */ #endif /* _LIBCPU_IO_H_ */
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