URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [rtos/] [ucos-ii/] [2.91/] [ChangeLog-OR32] - Rev 812
Go to most recent revision | Compare with Previous | Blame | View Log
2011-05-17 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* ucos-port/os_cpu_c.c:
(OSTaskStkInit): Use ICE and DCE from current SR instead of
default to disable.
2011-04-20 Julius Baxter <julius@opencores.org>
* ucos-port/os_cpu_c.c:
(OSTaskStkInit): Made stack initialisation skip red zone (128 bytes).
* ucos-port/os_cpu_a.S:
(UserISR): Fix register used on entry. (submitted by user keviny)
2011-01-14 Julius Baxter <julius@opencores.org>
* config.mk: <LDFLAGS>: Added entry point at 0x100 (decimal 256).
2011-01-11 Julius Baxter <julius@opencores.org>
* ucos-port/: Created.
* tasks/: Likewise.
* ucos/os_cpu_c.c: Moved to ucos-port/
* os_cpu_a.S: Moved to ucos-port/
* common/cprintf_r.c: Added.
* ucos-port/Makefile: Likewise.
* tasks/Makefile: Likewise.
* include/cprintf_r.h: Likewise.
* drivers/console.c: Likewise.
* include/console.h: Likewise.
* tasks/tasks1.c: Likewise
* common/main.c:
(TaskStart): Added - calls hook for tasks code TaskStartCreateTasks.
(main): Changed printf to console_puts calls with loc. info.
* include/spr_defs: Removed.
* include/spr-defs: Added from latest or1ksim version.
2011-01-07 Julius Baxter <julius@opencores.org>
* ChangeLog-OR32: Created
* sim.cfg: MC disabled, flash memory removed, MMUs disabled, debug
disabled, CUC removed.
* os_cpu_a.S: Updated
* ram.ld: Added
* flash.ld: removed
* Makefile: Final link stage replaced with $(CC) instead of $(LD), it
finds libraries with greater ease.
* include/board.h: Removed all MC defines, flash boot options.
* include/os_cfg.h: Updated to version 2.91 (is default)
Go to most recent revision | Compare with Previous | Blame | View Log