Subversion Repositories openriscdevboard

#ifndef _SPIMASTER_H_
#define _SPIMASTER_H_
 
//memoryMap
#define SPI_MASTER_VERSION_REG 0x00
#define SPI_MASTER_CONTROL_REG 0x01
#define SPI_TRANS_TYPE_REG 0x02
#define SPI_TRANS_CTRL_REG 0x03
#define SPI_TRANS_STS_REG 0x04
#define SPI_TRANS_ERROR_REG 0x05
#define SPI_DIRECT_ACCESS_DATA_REG 0x06
#define SD_ADDR_7_0_REG 0x07
#define SD_ADDR_15_8_REG 0x08
#define SD_ADDR_23_16_REG 0x09
#define SD_ADDR_31_24_REG 0x0a
#define SPI_CLK_DEL_REG 0x0b
 
 
//FifoAddresses
#define SPI_RX_FIFO_DATA_REG 0x10
#define SPI_RX_FIFO_STATUS_REG 0x11
#define SPI_RX_FIFO_DATA_COUNT_MSB 0x12
#define SPI_RX_FIFO_DATA_COUNT_LSB 0x13
#define SPI_RX_FIFO_CONTROL_REG 0x14
#define SPI_TX_FIFO_DATA_REG 0x20
#define SPI_TX_FIFO_STATUS_REG 0x21
#define SPI_TX_FIFO_DATA_COUNT_MSB 0x22
#define SPI_TX_FIFO_DATA_COUNT_LSB 0x23
#define SPI_TX_FIFO_CONTROL_REG 0x24
 
#define NO_BLOCK_REQ 0x0
#define WRITE_SD_BLOCK 0x1
#define READ_SD_BLOCK 0x2
 
#define READ_NO_ERROR 0x0
#define READ_CMD_ERROR 0x1
#define READ_TOKEN_ERROR 0x2
 
#define WRITE_NO_ERROR 0x0
#define WRITE_CMD_ERROR 0x1
#define WRITE_DATA_ERROR 0x2
#define WRITE_BUSY_ERROR 0x3
 
 
#define TRANS_NOT_BUSY 0x00
#define TRANS_BUSY 0x01
 
#define SPI_TRANS_START 0x01
#define SPI_TRANS_STOP 0x00
 
#define SPI_DIRECT_ACCESS 0x00
#define SPI_INIT_SD 0x01
#define SPI_RW_READ_SD_BLOCK 0x02
#define SPI_RW_WRITE_SD_BLOCK 0x03
 
#define INIT_NO_ERROR 0x0
#define INIT_CMD0_ERROR 0x1
#define INIT_CMD1_ERROR 0x2
 
#define TX_FIFO_DEPTH 512
#define TX_FIFO_ADDR_WIDTH 9
#define RX_FIFO_DEPTH 512
#define RX_FIFO_ADDR_WIDTH 9
 
#endif /* _SPIMASTER_H_ */