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# VeriFLA Logic Analyzer Project File

# Serial port
# On Windows this would be COM5 or similar
#/dev/ttyUSB0
LA.portName=/dev/ttyUSB0
LA.baudRate=115200

# Memory
# ====
LA.memWords=64
# Data input width and indentical samples bits (clones) must be multiple of 8.
LA.dataWordLenBits=16
LA.clonesWordLenBits=8
LA.triggerMatchMemAddr=8


# Generated verilog
# ====
LA.timescaleUnit=1ns
LA.timescalePrecision=10ps
# clockPeriod expressed in [timescaleUnit]
LA.clockPeriod=20

# User data signals
LA.totalSignals=16
# Big endian (1) or Little endian (0).
LA.signalGroups=2
# Group 0
LA.groupName.0=cnta
LA.groupSize.0=8
LA.groupEndian.0=0
# Group 1
LA.groupName.1=cntb
LA.groupSize.1=8
LA.groupEndian.1=0