Subversion Repositories openverifla

# VeriFLA Logic Analyzer Project File

# Serial port
# On Windows this would be COM5 or similar
#/dev/ttyUSB0
LA.portName=/dev/ttyUSB0
LA.baudRate=115200

# Memory
# ====
LA.memWords=64
# Data input width and indentical samples bits (clones) must be multiple of 8.
LA.dataWordLenBits=16
LA.clonesWordLenBits=16
LA.triggerMatchMemAddr=8


# Generated verilog
# ====
LA.timescaleUnit=1ns
LA.timescalePrecision=10ps
# clockPeriod expressed in [timescaleUnit]
LA.clockPeriod=20

# User data signals
LA.totalSignals=16
# Big endian (1) or Little endian (0).
LA.signalGroups=4
# Group 0
LA.groupName.0=KBD_KEY
LA.groupSize.0=8
LA.groupEndian.0=0
# Group 1
LA.groupName.1=kbd_clk_line
LA.groupSize.1=1
LA.groupEndian.1=0
# Group 2
LA.groupName.2=kbd_data_line
LA.groupSize.2=1
LA.groupEndian.2=0
# Group 3
LA.groupName.3=not_used
LA.groupSize.3=6
LA.groupEndian.3=0