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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm4/] [or1200_top_cm4.twr] - Rev 2
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Release 11.1 Trace (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm4/ise_or1200_cm4/ise_or1200_cm4.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm4.twx or1200_top_cm4.ncd
-o or1200_top_cm4.twr or1200_top_cm4.pcf -ucf or1200_top_cm4.ucf
Design file: or1200_top_cm4.ncd
Physical constraint file: or1200_top_cm4.pcf
Device,package,speed: xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
WARNING:Timing:3223 - Timing constraint TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY
FROM TIMEGRP "clk_i" TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;
ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_1_clk_i_cml_3_ERROR =
MAXDELAY FROM TIMEGRP "clk_i_cml_1" TO TIMEGRP "clk_i_cml_3" 1 ns
DATAPATHONLY; ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_2_clk_i_ERROR = MAXDELAY
FROM TIMEGRP "clk_i_cml_2" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_3_clk_i_cml_1_ERROR =
MAXDELAY FROM TIMEGRP "clk_i_cml_3" TO TIMEGRP "clk_i_cml_1" 1 ns
DATAPATHONLY; ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_clk_i_cml_3_ERROR = MAXDELAY
FROM TIMEGRP "clk_i" TO TIMEGRP "clk_i_cml_3" 1 ns DATAPATHONLY;
ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY
FROM TIMEGRP "clk_i_cml_1" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_2_clk_i_cml_1_ERROR =
MAXDELAY FROM TIMEGRP "clk_i_cml_2" TO TIMEGRP "clk_i_cml_1" 1 ns
DATAPATHONLY; ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint TS_clk_i_cml_3_clk_i_cml_2_ERROR =
MAXDELAY FROM TIMEGRP "clk_i_cml_3" TO TIMEGRP "clk_i_cml_2" 1 ns
DATAPATHONLY; ignored during timing analysis.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
3242 timing errors detected. (3242 component switching limit errors)
Minimum period is 2.400ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_clk_i_ERROR = PERIOD TIMEGRP "clk_i" 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
Period: 1.000ns
High pulse: 0.500ns
High pulse limit: 1.200ns (Tospwh)
Physical resource: or1200_du/dbg_ack_o/SR
Logical resource: or1200_du/dbg_ack_o/SR
Location pin: OLOGIC_X1Y74.SR
Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
Period: 1.000ns
High pulse: 0.500ns
High pulse limit: 1.200ns (Tospwh)
Physical resource: dwb_biu/wb_adr_o_10_1/SR
Logical resource: dwb_biu/wb_adr_o_10_1/SR
Location pin: OLOGIC_X0Y89.SR
Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: -1.400ns (period - (min high pulse limit / (high pulse / period)))
Period: 1.000ns
High pulse: 0.500ns
High pulse limit: 1.200ns (Tospwh)
Physical resource: dwb_biu/wb_adr_o_11_1/SR
Logical resource: dwb_biu/wb_adr_o_11_1/SR
Location pin: OLOGIC_X0Y51.SR
Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns
HIGH 50%;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 0.818ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_clk_i_cml_1_ERROR = PERIOD TIMEGRP "clk_i_cml_1" 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
Period: 1.000ns
Low pulse: 0.500ns
Low pulse limit: 0.409ns (Tcl)
Physical resource: or1200_cpu/or1200_alu/result_csum_cml_1<3>/CLK
Logical resource: or1200_cpu/or1200_alu/result_csum_cml_1_0/CK
Location pin: SLICE_X4Y41.CLK
Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min high pulse limit / (high pulse / period)))
Period: 1.000ns
High pulse: 0.500ns
High pulse limit: 0.409ns (Tch)
Physical resource: or1200_cpu/or1200_alu/result_csum_cml_1<3>/CLK
Logical resource: or1200_cpu/or1200_alu/result_csum_cml_1_0/CK
Location pin: SLICE_X4Y41.CLK
Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
Period: 1.000ns
Low pulse: 0.500ns
Low pulse limit: 0.409ns (Tcl)
Physical resource: or1200_cpu/or1200_alu/result_csum_cml_1<3>/CLK
Logical resource: or1200_cpu/or1200_alu/result_csum_cml_1_1/CK
Location pin: SLICE_X4Y41.CLK
Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns
HIGH 50%;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 0.818ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_clk_i_cml_2_ERROR = PERIOD TIMEGRP "clk_i_cml_2" 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
Period: 1.000ns
Low pulse: 0.500ns
Low pulse limit: 0.409ns (Tcl)
Physical resource: or1200_cpu/or1200_rf/datab_saved_cml_2<7>/CLK
Logical resource: or1200_cpu/or1200_rf/datab_saved_cml_2_4/CK
Location pin: SLICE_X0Y28.CLK
Clock network: clk_i_cml_2_BUFGP
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min high pulse limit / (high pulse / period)))
Period: 1.000ns
High pulse: 0.500ns
High pulse limit: 0.409ns (Tch)
Physical resource: or1200_cpu/or1200_rf/datab_saved_cml_2<7>/CLK
Logical resource: or1200_cpu/or1200_rf/datab_saved_cml_2_4/CK
Location pin: SLICE_X0Y28.CLK
Clock network: clk_i_cml_2_BUFGP
--------------------------------------------------------------------------------
Slack: 0.182ns (period - (min low pulse limit / (low pulse / period)))
Period: 1.000ns
Low pulse: 0.500ns
Low pulse limit: 0.409ns (Tcl)
Physical resource: or1200_cpu/or1200_rf/datab_saved_cml_2<7>/CLK
Logical resource: or1200_cpu/or1200_rf/datab_saved_cml_2_5/CK
Location pin: SLICE_X0Y28.CLK
Clock network: clk_i_cml_2_BUFGP
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_3_ERROR = PERIOD TIMEGRP "clk_i_cml_3" 1 ns
HIGH 50%;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 1.000ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_clk_i_cml_3_ERROR = PERIOD TIMEGRP "clk_i_cml_3" 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 0.000ns (period - (min low pulse limit / (low pulse / period)))
Period: 1.000ns
Low pulse: 0.500ns
Low pulse limit: 0.500ns (Tockpwl)
Physical resource: or1200_pic/intr_cml_3_1/CLK
Logical resource: or1200_pic/intr_cml_3_1/CK
Location pin: OLOGIC_X2Y89.CLK
Clock network: clk_i_cml_3_BUFGP
--------------------------------------------------------------------------------
Slack: 0.000ns (period - (min high pulse limit / (high pulse / period)))
Period: 1.000ns
High pulse: 0.500ns
High pulse limit: 0.500ns (Tockpwh)
Physical resource: or1200_pic/intr_cml_3_1/CLK
Logical resource: or1200_pic/intr_cml_3_1/CK
Location pin: OLOGIC_X2Y89.CLK
Clock network: clk_i_cml_3_BUFGP
--------------------------------------------------------------------------------
Slack: 0.000ns (period - min period limit)
Period: 1.000ns
Min period limit: 1.000ns (1000.000MHz) (Tockper)
Physical resource: or1200_pic/intr_cml_3_1/CLK
Logical resource: or1200_pic/intr_cml_3_1/CK
Location pin: OLOGIC_X2Y89.CLK
Clock network: clk_i_cml_3_BUFGP
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_clk_i_cml_2_ERROR = MAXDELAY FROM TIMEGRP "clk_i"
TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_1_clk_i_cml_3_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_1" TO TIMEGRP "clk_i_cml_3" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_2_clk_i_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_2" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_3_clk_i_cml_1_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_3" TO TIMEGRP "clk_i_cml_1" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_clk_i_cml_3_ERROR = MAXDELAY FROM TIMEGRP "clk_i"
TO TIMEGRP "clk_i_cml_3" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_1_clk_i_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_1" TO TIMEGRP "clk_i" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_2_clk_i_cml_1_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_2" TO TIMEGRP "clk_i_cml_1" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_i_cml_3_clk_i_cml_2_ERROR = MAXDELAY FROM TIMEGRP
"clk_i_cml_3" TO TIMEGRP "clk_i_cml_2" 1 ns DATAPATHONLY;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.
Timing summary:
---------------
Timing errors: 3242 Score: 922706 (Setup/Max: 0, Hold: 0, Component Switching Limit: 922706)
Constraints cover 0 paths, 0 nets, and 0 connections
Design statistics:
Minimum period: 2.400ns{1} (Maximum frequency: 416.667MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Thu Oct 21 17:06:02 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 327 MB