Subversion Repositories or1200_hp

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Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm4_top/ise_or1200_cm4_top/ise_or1200_cm4_top.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm4_top.twx
or1200_top_cm4_top.ncd -o or1200_top_cm4_top.twr or1200_top_cm4_top.pcf -ucf
or1200_top_cm4_top.ucf

Design file:              or1200_top_cm4_top.ncd
Physical constraint file: or1200_top_cm4_top.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 3.7632 ns HIGH 50%;

 116812 paths analyzed, 16070 endpoints analyzed, 2562 failing endpoints
 2562 timing errors detected. (2562 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   5.279ns.
--------------------------------------------------------------------------------
Slack (setup path):     -1.516ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP (RAM)
  Destination:          or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1 (FF)
  Requirement:          3.763ns
  Data Path Delay:      4.902ns (Levels of Logic = 1)
  Clock Path Skew:      -0.342ns (1.111 - 1.453)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 3.763ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP to or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y10.DOBDOU1 Trcko_DORB            2.180   or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
                                                       or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
    SLICE_X35Y51.B4      net (fanout=1)        1.794   or1200_top_cm4i/or1200_ic_top/tag<11>
    SLICE_X35Y51.B       Tilo                  0.094   or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
                                                       or1200_top_cm4i/or1200_ic_top/tag_comp_2_SW0
    SLICE_X35Y51.SR      net (fanout=1)        0.289   N481
    SLICE_X35Y51.CLK     Tsrck                 0.545   or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
                                                       or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      4.902ns (2.819ns logic, 2.083ns route)
                                                       (57.5% logic, 42.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     -1.387ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP (RAM)
  Destination:          or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1 (FF)
  Requirement:          3.763ns
  Data Path Delay:      4.786ns (Levels of Logic = 1)
  Clock Path Skew:      -0.329ns (1.111 - 1.440)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 3.763ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP to or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y10.DOBDOL2 Trcko_DORB            2.180   or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
                                                       or1200_top_cm4i/or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
    SLICE_X35Y51.B5      net (fanout=1)        1.678   or1200_top_cm4i/or1200_ic_top/tag<12>
    SLICE_X35Y51.B       Tilo                  0.094   or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
                                                       or1200_top_cm4i/or1200_ic_top/tag_comp_2_SW0
    SLICE_X35Y51.SR      net (fanout=1)        0.289   N481
    SLICE_X35Y51.CLK     Tsrck                 0.545   or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
                                                       or1200_top_cm4i/or1200_ic_top/tag_comp_2_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      4.786ns (2.819ns logic, 1.967ns route)
                                                       (58.9% logic, 41.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     -1.360ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_top_cm4i/or1200_cpu/or1200_operandmuxes/operand_a_31 (FF)
  Destination:          or1200_top_cm4i/or1200_cpu/or1200_alu/shifted_rotated_cml_1_16 (FF)
  Requirement:          3.763ns
  Data Path Delay:      4.946ns (Levels of Logic = 3)
  Clock Path Skew:      -0.142ns (1.211 - 1.353)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 3.763ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_top_cm4i/or1200_cpu/or1200_operandmuxes/operand_a_31 to or1200_top_cm4i/or1200_cpu/or1200_alu/shifted_rotated_cml_1_16
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y58.CQ       Tcko                  0.471   or1200_top_cm4i/or1200_cpu/or1200_operandmuxes/operand_a<31>
                                                       or1200_top_cm4i/or1200_cpu/or1200_operandmuxes/operand_a_31
    SLICE_X1Y52.B1       net (fanout=34)       1.607   or1200_top_cm4i/or1200_cpu/or1200_operandmuxes/operand_a<31>
    SLICE_X1Y52.B        Tilo                  0.094   or1200_top_cm4i/or1200_cpu/or1200_alu/Sh28
                                                       or1200_top_cm4i/or1200_cpu/or1200_alu/Sh281
    SLICE_X0Y69.B5       net (fanout=5)        1.284   or1200_top_cm4i/or1200_cpu/or1200_alu/Sh28
    SLICE_X0Y69.B        Tilo                  0.094   or1200_top_cm4i/or1200_cpu/or1200_wbmux/muxreg_valid_cml_3
                                                       or1200_top_cm4i/or1200_cpu/or1200_alu/Sh481
    SLICE_X0Y69.C3       net (fanout=2)        0.464   or1200_top_cm4i/or1200_cpu/or1200_alu/Sh48
    SLICE_X0Y69.C        Tilo                  0.094   or1200_top_cm4i/or1200_cpu/or1200_wbmux/muxreg_valid_cml_3
                                                       or1200_top_cm4i/or1200_cpu/or1200_alu/shifted_rotated<16>8
    SLICE_X1Y69.SR       net (fanout=1)        0.291   or1200_top_cm4i/or1200_cpu/or1200_alu/shifted_rotated<16>8
    SLICE_X1Y69.CLK      Tsrck                 0.547   or1200_top_cm4i/or1200_cpu/or1200_alu/shifted_rotated_cml_1<16>
                                                       or1200_top_cm4i/or1200_cpu/or1200_alu/shifted_rotated_cml_1_16
    -------------------------------------------------  ---------------------------
    Total                                      4.946ns (1.300ns logic, 3.646ns route)
                                                       (26.3% logic, 73.7% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 3.7632 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.307ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm4i/or1200_immu_top/icpu_vpn_r_29 (FF)
  Destination:          or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1_29 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.318ns (Levels of Logic = 0)
  Clock Path Skew:      0.011ns (0.170 - 0.159)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 3.763ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm4i/or1200_immu_top/icpu_vpn_r_29 to or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1_29
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X41Y43.AQ      Tcko                  0.414   or1200_top_cm4i/or1200_immu_top/icpu_vpn_r<31>
                                                       or1200_top_cm4i/or1200_immu_top/icpu_vpn_r_29
    SLICE_X40Y43.BX      net (fanout=1)        0.146   or1200_top_cm4i/or1200_immu_top/icpu_vpn_r<29>
    SLICE_X40Y43.CLK     Tckdi       (-Th)     0.242   or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1<31>
                                                       or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1_29
    -------------------------------------------------  ---------------------------
    Total                                      0.318ns (0.172ns logic, 0.146ns route)
                                                       (54.1% logic, 45.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.309ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm4i/or1200_immu_top/icpu_vpn_r_17 (FF)
  Destination:          or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1_17 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.349ns (Levels of Logic = 0)
  Clock Path Skew:      0.040ns (0.202 - 0.162)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 3.763ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm4i/or1200_immu_top/icpu_vpn_r_17 to or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1_17
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y42.AQ      Tcko                  0.414   or1200_top_cm4i/or1200_immu_top/icpu_vpn_r<20>
                                                       or1200_top_cm4i/or1200_immu_top/icpu_vpn_r_17
    SLICE_X38Y42.BX      net (fanout=1)        0.166   or1200_top_cm4i/or1200_immu_top/icpu_vpn_r<17>
    SLICE_X38Y42.CLK     Tckdi       (-Th)     0.231   or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1<19>
                                                       or1200_top_cm4i/or1200_cpu/or1200_genpc/icpu_adr_i_cml_1_17
    -------------------------------------------------  ---------------------------
    Total                                      0.349ns (0.183ns logic, 0.166ns route)
                                                       (52.4% logic, 47.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.310ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_top_cm4i/or1200_du/drr_9 (FF)
  Destination:          or1200_top_cm4i/or1200_du/drr_cml_1_9 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.349ns (Levels of Logic = 0)
  Clock Path Skew:      0.039ns (0.194 - 0.155)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 3.763ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_top_cm4i/or1200_du/drr_9 to or1200_top_cm4i/or1200_du/drr_cml_1_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y56.AQ      Tcko                  0.414   or1200_top_cm4i/or1200_du/drr<11>
                                                       or1200_top_cm4i/or1200_du/drr_9
    SLICE_X42Y56.BX      net (fanout=1)        0.166   or1200_top_cm4i/or1200_du/drr<9>
    SLICE_X42Y56.CLK     Tckdi       (-Th)     0.231   or1200_top_cm4i/or1200_du/drr_cml_1<11>
                                                       or1200_top_cm4i/or1200_du/drr_cml_1_9
    -------------------------------------------------  ---------------------------
    Total                                      0.349ns (0.183ns logic, 0.166ns route)
                                                       (52.4% logic, 47.6% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 3.7632 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.362ns (period - (min high pulse limit / (high pulse / period)))
  Period: 3.763ns
  High pulse: 1.881ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm4i/iwb_biu/wb_sel_o<0>/SR
  Logical resource: or1200_top_cm4i/iwb_biu/wb_sel_o_0/SR
  Location pin: OLOGIC_X2Y40.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 1.362ns (period - (min high pulse limit / (high pulse / period)))
  Period: 3.763ns
  High pulse: 1.881ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm4i/iwb_biu/wb_sel_o_0_3/SR
  Logical resource: or1200_top_cm4i/iwb_biu/wb_sel_o_0_3/SR
  Location pin: OLOGIC_X2Y57.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 1.362ns (period - (min high pulse limit / (high pulse / period)))
  Period: 3.763ns
  High pulse: 1.881ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_top_cm4i/iwb_biu/wb_sel_o_0_2/SR
  Logical resource: or1200_top_cm4i/iwb_biu/wb_sel_o_0_2/SR
  Location pin: OLOGIC_X0Y195.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_i          |    5.279|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 2562  Score: 1058748  (Setup/Max: 1058748, Hold: 0)

Constraints cover 116812 paths, 0 nets, and 27747 connections

Design statistics:
   Minimum period:   5.279ns{1}   (Maximum frequency: 189.430MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Oct 21 18:22:41 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 348 MB