Subversion Repositories or1200_hp

--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_orig/ise_or1200_orig/ise_or1200_orig.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top.twx or1200_top.ncd -o
or1200_top.twr or1200_top.pcf -ucf or1200_top.ucf

Design file:              or1200_top.ncd
Physical constraint file: or1200_top.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 13.5 ns HIGH 50%;

 82773042 paths analyzed, 7275 endpoints analyzed, 218 failing endpoints
 218 timing errors detected. (218 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  14.169ns.
--------------------------------------------------------------------------------
Slack (setup path):     -0.669ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (RAM)
  Destination:          or1200_cpu/or1200_ctrl/spr_addrimm_6_1 (FF)
  Requirement:          13.500ns
  Data Path Delay:      13.853ns (Levels of Logic = 12)
  Clock Path Skew:      -0.281ns (1.109 - 1.390)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 13.500ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP to or1200_cpu/or1200_ctrl/spr_addrimm_6_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X1Y6.DOADOL8  Trcko_DO              2.180   or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
                                                       or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
    SLICE_X42Y29.B4      net (fanout=1)        0.915   or1200_ic_top/tag<4>
    SLICE_X42Y29.COUT    Topcyb                0.501   or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_lut<1>
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X42Y30.CIN     net (fanout=1)        0.010   or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X42Y30.CMUX    Tcinc                 0.352   or1200_ic_top/tagcomp_miss
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X43Y47.A6      net (fanout=22)       1.376   or1200_ic_top/tagcomp_miss
    SLICE_X43Y47.A       Tilo                  0.094   iwb_biu/aborted_r
                                                       or1200_ic_top/icqmem_ack_o1
    SLICE_X41Y52.C6      net (fanout=71)       0.653   icqmem_ack_ic
    SLICE_X41Y52.C       Tilo                  0.094   or1200_immu_top/dis_spr_access
                                                       or1200_cpu/or1200_genpc/icpu_adr_o_and00001
    SLICE_X45Y50.D6      net (fanout=64)       0.791   or1200_cpu/or1200_genpc/icpu_adr_o_and0000
    SLICE_X45Y50.D       Tilo                  0.094   or1200_immu_top/icpu_vpn_r<16>
                                                       or1200_cpu/or1200_genpc/icpu_adr_o<16>1
    SLICE_X44Y45.B4      net (fanout=1)        0.869   icpu_adr_cpu<16>
    SLICE_X44Y45.COUT    Topcyb                0.483   or1200_immu_top/Mcompar_page_cross_cy<3>
                                                       or1200_immu_top/Mcompar_page_cross_lut<1>
                                                       or1200_immu_top/Mcompar_page_cross_cy<3>
    SLICE_X44Y46.CIN     net (fanout=1)        0.000   or1200_immu_top/Mcompar_page_cross_cy<3>
    SLICE_X44Y46.CMUX    Tcinc                 0.358   or1200_immu_top/page_cross
                                                       or1200_immu_top/Mcompar_page_cross_cy<6>
    SLICE_X45Y63.A6      net (fanout=46)       1.258   or1200_immu_top/page_cross
    SLICE_X45Y63.A       Tilo                  0.094   N912
                                                       or1200_cpu/or1200_if/if_stall1
    SLICE_X45Y63.C6      net (fanout=12)       0.353   or1200_cpu/if_stall
    SLICE_X45Y63.C       Tilo                  0.094   N912
                                                       or1200_cpu/or1200_freeze/wb_freeze1
    SLICE_X45Y65.C6      net (fanout=112)      0.408   ex_freeze
    SLICE_X45Y65.C       Tilo                  0.094   or1200_cpu/or1200_ctrl/alu_op_2_1
                                                       or1200_cpu/or1200_except/epcr_mux0000<0>3
    SLICE_X46Y59.B6      net (fanout=342)      1.101   or1200_cpu/or1200_except/N01
    SLICE_X46Y59.B       Tilo                  0.094   or1200_cpu/or1200_ctrl/id_insn<23>
                                                       or1200_cpu/or1200_except/flushpipe1
    SLICE_X40Y61.C6      net (fanout=98)       0.999   or1200_cpu/flushpipe
    SLICE_X40Y61.C       Tilo                  0.094   or1200_cpu/or1200_ctrl/spr_addrimm<7>
                                                       or1200_cpu/or1200_ctrl/spr_addrimm_6_rstpot
    SLICE_X32Y61.AX      net (fanout=1)        0.506   or1200_cpu/or1200_ctrl/spr_addrimm_6_rstpot
    SLICE_X32Y61.CLK     Tdick                -0.012   or1200_cpu/or1200_ctrl/spr_addrimm_6_1
                                                       or1200_cpu/or1200_ctrl/spr_addrimm_6_1
    -------------------------------------------------  ---------------------------
    Total                                     13.853ns (4.614ns logic, 9.239ns route)
                                                       (33.3% logic, 66.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.632ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (RAM)
  Destination:          or1200_cpu/or1200_ctrl/alu_op_1_1 (FF)
  Requirement:          13.500ns
  Data Path Delay:      13.852ns (Levels of Logic = 12)
  Clock Path Skew:      -0.245ns (1.145 - 1.390)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 13.500ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP to or1200_cpu/or1200_ctrl/alu_op_1_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X1Y6.DOADOL8  Trcko_DO              2.180   or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
                                                       or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
    SLICE_X42Y29.B4      net (fanout=1)        0.915   or1200_ic_top/tag<4>
    SLICE_X42Y29.COUT    Topcyb                0.501   or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_lut<1>
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X42Y30.CIN     net (fanout=1)        0.010   or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X42Y30.CMUX    Tcinc                 0.352   or1200_ic_top/tagcomp_miss
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X43Y47.A6      net (fanout=22)       1.376   or1200_ic_top/tagcomp_miss
    SLICE_X43Y47.A       Tilo                  0.094   iwb_biu/aborted_r
                                                       or1200_ic_top/icqmem_ack_o1
    SLICE_X41Y52.C6      net (fanout=71)       0.653   icqmem_ack_ic
    SLICE_X41Y52.C       Tilo                  0.094   or1200_immu_top/dis_spr_access
                                                       or1200_cpu/or1200_genpc/icpu_adr_o_and00001
    SLICE_X45Y50.D6      net (fanout=64)       0.791   or1200_cpu/or1200_genpc/icpu_adr_o_and0000
    SLICE_X45Y50.D       Tilo                  0.094   or1200_immu_top/icpu_vpn_r<16>
                                                       or1200_cpu/or1200_genpc/icpu_adr_o<16>1
    SLICE_X44Y45.B4      net (fanout=1)        0.869   icpu_adr_cpu<16>
    SLICE_X44Y45.COUT    Topcyb                0.483   or1200_immu_top/Mcompar_page_cross_cy<3>
                                                       or1200_immu_top/Mcompar_page_cross_lut<1>
                                                       or1200_immu_top/Mcompar_page_cross_cy<3>
    SLICE_X44Y46.CIN     net (fanout=1)        0.000   or1200_immu_top/Mcompar_page_cross_cy<3>
    SLICE_X44Y46.CMUX    Tcinc                 0.358   or1200_immu_top/page_cross
                                                       or1200_immu_top/Mcompar_page_cross_cy<6>
    SLICE_X45Y63.A6      net (fanout=46)       1.258   or1200_immu_top/page_cross
    SLICE_X45Y63.A       Tilo                  0.094   N912
                                                       or1200_cpu/or1200_if/if_stall1
    SLICE_X45Y63.C6      net (fanout=12)       0.353   or1200_cpu/if_stall
    SLICE_X45Y63.C       Tilo                  0.094   N912
                                                       or1200_cpu/or1200_freeze/wb_freeze1
    SLICE_X45Y65.C6      net (fanout=112)      0.408   ex_freeze
    SLICE_X45Y65.C       Tilo                  0.094   or1200_cpu/or1200_ctrl/alu_op_2_1
                                                       or1200_cpu/or1200_except/epcr_mux0000<0>3
    SLICE_X46Y59.B6      net (fanout=342)      1.101   or1200_cpu/or1200_except/N01
    SLICE_X46Y59.B       Tilo                  0.094   or1200_cpu/or1200_ctrl/id_insn<23>
                                                       or1200_cpu/or1200_except/flushpipe1
    SLICE_X34Y63.A6      net (fanout=98)       1.153   or1200_cpu/flushpipe
    SLICE_X34Y63.A       Tilo                  0.094   or1200_cpu/or1200_ctrl/alu_op<1>
                                                       or1200_cpu/or1200_ctrl/alu_op_1_rstpot
    SLICE_X34Y61.DX      net (fanout=1)        0.337   or1200_cpu/or1200_ctrl/alu_op_1_rstpot
    SLICE_X34Y61.CLK     Tdick                 0.002   or1200_cpu/or1200_ctrl/alu_op_1_1
                                                       or1200_cpu/or1200_ctrl/alu_op_1_1
    -------------------------------------------------  ---------------------------
    Total                                     13.852ns (4.628ns logic, 9.224ns route)
                                                       (33.4% logic, 66.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.590ns (requirement - (data path - clock path skew + uncertainty))
  Source:               or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (RAM)
  Destination:          or1200_cpu/or1200_ctrl/spr_addrimm_5_1 (FF)
  Requirement:          13.500ns
  Data Path Delay:      13.810ns (Levels of Logic = 12)
  Clock Path Skew:      -0.245ns (1.145 - 1.390)
  Source Clock:         clk_i_BUFGP rising at 0.000ns
  Destination Clock:    clk_i_BUFGP rising at 13.500ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP to or1200_cpu/or1200_ctrl/spr_addrimm_5_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X1Y6.DOADOL8  Trcko_DO              2.180   or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
                                                       or1200_ic_top/or1200_ic_tag/ic_tag0/ic_tag_blki/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP
    SLICE_X42Y29.B4      net (fanout=1)        0.915   or1200_ic_top/tag<4>
    SLICE_X42Y29.COUT    Topcyb                0.501   or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_lut<1>
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X42Y30.CIN     net (fanout=1)        0.010   or1200_ic_top/tagcomp_miss_or0000_wg_cy<3>
    SLICE_X42Y30.CMUX    Tcinc                 0.352   or1200_ic_top/tagcomp_miss
                                                       or1200_ic_top/tagcomp_miss_or0000_wg_cy<6>
    SLICE_X43Y47.A6      net (fanout=22)       1.376   or1200_ic_top/tagcomp_miss
    SLICE_X43Y47.A       Tilo                  0.094   iwb_biu/aborted_r
                                                       or1200_ic_top/icqmem_ack_o1
    SLICE_X41Y52.C6      net (fanout=71)       0.653   icqmem_ack_ic
    SLICE_X41Y52.C       Tilo                  0.094   or1200_immu_top/dis_spr_access
                                                       or1200_cpu/or1200_genpc/icpu_adr_o_and00001
    SLICE_X45Y50.D6      net (fanout=64)       0.791   or1200_cpu/or1200_genpc/icpu_adr_o_and0000
    SLICE_X45Y50.D       Tilo                  0.094   or1200_immu_top/icpu_vpn_r<16>
                                                       or1200_cpu/or1200_genpc/icpu_adr_o<16>1
    SLICE_X44Y45.B4      net (fanout=1)        0.869   icpu_adr_cpu<16>
    SLICE_X44Y45.COUT    Topcyb                0.483   or1200_immu_top/Mcompar_page_cross_cy<3>
                                                       or1200_immu_top/Mcompar_page_cross_lut<1>
                                                       or1200_immu_top/Mcompar_page_cross_cy<3>
    SLICE_X44Y46.CIN     net (fanout=1)        0.000   or1200_immu_top/Mcompar_page_cross_cy<3>
    SLICE_X44Y46.CMUX    Tcinc                 0.358   or1200_immu_top/page_cross
                                                       or1200_immu_top/Mcompar_page_cross_cy<6>
    SLICE_X45Y63.A6      net (fanout=46)       1.258   or1200_immu_top/page_cross
    SLICE_X45Y63.A       Tilo                  0.094   N912
                                                       or1200_cpu/or1200_if/if_stall1
    SLICE_X45Y63.C6      net (fanout=12)       0.353   or1200_cpu/if_stall
    SLICE_X45Y63.C       Tilo                  0.094   N912
                                                       or1200_cpu/or1200_freeze/wb_freeze1
    SLICE_X45Y65.C6      net (fanout=112)      0.408   ex_freeze
    SLICE_X45Y65.C       Tilo                  0.094   or1200_cpu/or1200_ctrl/alu_op_2_1
                                                       or1200_cpu/or1200_except/epcr_mux0000<0>3
    SLICE_X46Y59.B6      net (fanout=342)      1.101   or1200_cpu/or1200_except/N01
    SLICE_X46Y59.B       Tilo                  0.094   or1200_cpu/or1200_ctrl/id_insn<23>
                                                       or1200_cpu/or1200_except/flushpipe1
    SLICE_X40Y61.B5      net (fanout=98)       0.918   or1200_cpu/flushpipe
    SLICE_X40Y61.B       Tilo                  0.094   or1200_cpu/or1200_ctrl/spr_addrimm<7>
                                                       or1200_cpu/or1200_ctrl/spr_addrimm_5_rstpot
    SLICE_X34Y61.AX      net (fanout=1)        0.540   or1200_cpu/or1200_ctrl/spr_addrimm_5_rstpot
    SLICE_X34Y61.CLK     Tdick                -0.008   or1200_cpu/or1200_ctrl/alu_op_1_1
                                                       or1200_cpu/or1200_ctrl/spr_addrimm_5_1
    -------------------------------------------------  ---------------------------
    Total                                     13.810ns (4.618ns logic, 9.192ns route)
                                                       (33.4% logic, 66.6% route)

--------------------------------------------------------------------------------

Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 13.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.309ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0 (FF)
  Destination:          or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_33 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.318ns (Levels of Logic = 0)
  Clock Path Skew:      0.009ns (0.150 - 0.141)
  Source Clock:         clk_i_BUFGP rising at 13.500ns
  Destination Clock:    clk_i_BUFGP rising at 13.500ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0 to or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_33
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y105.AQ     Tcko                  0.414   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_3
                                                       or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0
    SLICE_X12Y105.BX     net (fanout=1)        0.146   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_0
    SLICE_X12Y105.CLK    Tckdi       (-Th)     0.242   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1<35>
                                                       or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_33
    -------------------------------------------------  ---------------------------
    Total                                      0.318ns (0.172ns logic, 0.146ns route)
                                                       (54.1% logic, 45.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.312ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7 (FF)
  Destination:          or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_26 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.350ns (Levels of Logic = 0)
  Clock Path Skew:      0.038ns (0.174 - 0.136)
  Source Clock:         clk_i_BUFGP rising at 13.500ns
  Destination Clock:    clk_i_BUFGP rising at 13.500ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7 to or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_26
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y95.DQ      Tcko                  0.414   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7
                                                       or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7
    SLICE_X18Y95.CX      net (fanout=1)        0.154   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_7
    SLICE_X18Y95.CLK     Tckdi       (-Th)     0.218   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1<27>
                                                       or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_26
    -------------------------------------------------  ---------------------------
    Total                                      0.350ns (0.196ns logic, 0.154ns route)
                                                       (56.0% logic, 44.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.315ns (requirement - (clock path skew + uncertainty - data path))
  Source:               or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1 (FF)
  Destination:          or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_32 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.324ns (Levels of Logic = 0)
  Clock Path Skew:      0.009ns (0.150 - 0.141)
  Source Clock:         clk_i_BUFGP rising at 13.500ns
  Destination Clock:    clk_i_BUFGP rising at 13.500ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1 to or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_32
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y105.BQ     Tcko                  0.414   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_3
                                                       or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1
    SLICE_X12Y105.AX     net (fanout=1)        0.146   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/Mmult_p0_mult00005_1
    SLICE_X12Y105.CLK    Tckdi       (-Th)     0.236   or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1<35>
                                                       or1200_cpu/or1200_mult_mac/or1200_gmultp2_32x32/p1_32
    -------------------------------------------------  ---------------------------
    Total                                      0.324ns (0.178ns logic, 0.146ns route)
                                                       (54.9% logic, 45.1% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 13.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 11.100ns (period - (min high pulse limit / (high pulse / period)))
  Period: 13.500ns
  High pulse: 6.750ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_du/dbg_ack_o/SR
  Logical resource: or1200_du/dbg_ack_o/SR
  Location pin: OLOGIC_X2Y199.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 11.100ns (period - (min high pulse limit / (high pulse / period)))
  Period: 13.500ns
  High pulse: 6.750ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: iwb_biu/wb_sel_o<3>/SR
  Logical resource: iwb_biu/wb_sel_o_3/SR
  Location pin: OLOGIC_X2Y164.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 11.100ns (period - (min high pulse limit / (high pulse / period)))
  Period: 13.500ns
  High pulse: 6.750ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: iwb_biu/wb_sel_o_3_3/SR
  Logical resource: iwb_biu/wb_sel_o_3_3/SR
  Location pin: OLOGIC_X0Y62.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_i          |   14.169|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 218  Score: 38142  (Setup/Max: 38142, Hold: 0)

Constraints cover 82773042 paths, 0 nets, and 18525 connections

Design statistics:
   Minimum period:  14.169ns{1}   (Maximum frequency:  70.577MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sun Oct 17 21:17:55 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 302 MB