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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file dtlb_mr_blk.v when simulating
// the core, dtlb_mr_blk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
module dtlb_mr_sub_cm3(
		clk_i_cml_1,
		clk_i_cml_2,
		cmls,
 
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);
 
 
input clk_i_cml_1;
input clk_i_cml_2;
input [1:0] cmls;
 
 
 
 
input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;
 
wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;
 
assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;
 
dtlb_mr_blk_cm3 dtlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));
 
endmodule