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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file rf_blk.v when simulating
// the core, rf_blk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
`timescale 1ns/1ps
 
 
module rf_sub_cm3_22(
		clk_i_cml_2,
		cmls,
 
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);
 
 
input clk_i_cml_2;
input [1:0] cmls;
 
reg [ 4 : 0 ] a_cml_2;
 
 
 
input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
 
rf_dist_cm3 rf_disti(
	.a({cmls, a_cml_2}),
	.d(d),
	.dpra({cmls, dpra}),
	.clk(clk),
	.we(we),
	.spo(spo),
	.dpo(dpo));
 
always @ (posedge clk_i_cml_2) begin
a_cml_2 <= a;
end
 
endmodule
 
module rf_sub_cm3_24(
		clk_i_cml_2,
		cmls,
 
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);
 
 
input clk_i_cml_2;
input [1:0] cmls;
 
reg [ 4 : 0 ] a_cml_2;
 
 
 
input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
 
rf_dist_cm3 rf_disti(
	.a({cmls, a_cml_2}),
	.d(d),
	.dpra({cmls, dpra}),
	.clk(clk),
	.we(we),
	.spo(spo),
	.dpo(dpo));
 
always @ (posedge clk_i_cml_2) begin
a_cml_2 <= a;
end
 
endmodule
 
 
module rf_sub_cm3(
		cmls,
 
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);
 
 
input [1:0] cmls;
 
 
 
 
input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
 
rf_dist_cm3 rf_disti(
	.a(a),
	.d(d),
	.dpra(dpra),
	.clk(clk),
	.we(we),
	.spo(spo),
	.dpo(dpo));
 
 
endmodule