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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
 
// You must compile the wrapper file rf_dist.v when simulating
// the core, rf_dist. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module rf_dist(
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);
 
 
input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
 
reg	[31:0]		mem [31:0];
 
integer i;
initial begin
	for (i = 0; i < 32; i = i + 1) begin
		mem[i] <= 32'h0;
	end
end
 
//
// Write port
//
always @(posedge clk)
	if (we) mem[a] <= #1 d;
 
//
// Read port A
//
 
assign spo = mem[a];
assign dpo = mem[dpra];
 
endmodule