Subversion Repositories or1200_soc

[Library]

; Altera specific primitive library mappings 

vital2000 = $MODEL_TECH/../vital2000
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
std = $MODEL_TECH/../std
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
apex20k = $MODEL_TECH/../altera/vhdl/apex20k
apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
apexii = $MODEL_TECH/../altera/vhdl/apexii
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
max = $MODEL_TECH/../altera/vhdl/max
maxii = $MODEL_TECH/../altera/vhdl/maxii
stratix = $MODEL_TECH/../altera/vhdl/stratix
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
hcstratix = $MODEL_TECH/../altera/vhdl/hcstratix
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
sgate = $MODEL_TECH/../altera/vhdl/sgate
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
apexii_ver = $MODEL_TECH/../altera/verilog/apexii
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
max_ver = $MODEL_TECH/../altera/verilog/max
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
hcstratix_ver = $MODEL_TECH/../altera/verilog/hcstratix
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
work = or1200
[vcom]
; Turn on VHDL-1993 as the default. Normally is off.
; VHDL93 = 1

; Show source line containing error. Default is off.
; Show_source = 1

; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; .ini file has Explict enable so that std_logic_signed/unsigned
; will match synthesis tools behavior.
 Explicit = 1

; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = false

; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1

; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1

; Turn off "loading..." messages. Default is messages on.
; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:
;       -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1

; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.

; RequireConfigForAllDefaultBinding = 1 

[vlog]

; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1

; Turn off "loading..." messages. Default is messages on.
; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1

; Turns on incremental compilation of modules 
; Incremental = 1

[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps

; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
UserTimeUnit = default

; Default run length
RunLength = 100

; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000

; Directive to license manager:
; vhdl          Immediately reserve a VHDL license
; vlog          Immediately reserve a Verilog license
; plus          Immediately reserve a VHDL and Verilog license
; nomgc         Do not look for Mentor Graphics Licenses
; nomti         Do not look for Model Technology Licenses
; noqueue       Do not wait in the license queue when a license isn't available
; License = plus

; Stop the simulator after an assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; Assertion Message Format
; %S - Severity Level 
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; Assertion File - alternate file for storing assertion messages
; AssertFile = assert.log

; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic

; VSIM Startup command
; Startup = do startup.do

; File for saving command transcript
TranscriptFile = transcript

; File for saving command history 
;CommandHistory = cmdhist.log

; Specify whether paths in simulator commands should be described 
; in VHDL or Verilog format. For VHDL, PathSeparator = /
; for Verilog, PathSeparator = .
PathSeparator = /

; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :

; Disable assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1

; Default force kind. May be freeze, drive, or deposit 
; or in other terms, fixed, wired or charged.
; DefaultForceKind = freeze

; If zero, open files when elaborated
; else open files on first read or write
; DelayFileOpen = 0

; Control VHDL files opened for write
;   0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0

; Control number of VHDL files open concurrently
;   This number should always be less then the 
;   current ulimit setting for max file descriptors
;   0 = unlimited
ConcurrentFileLimit = 40

; This controls the number of hierarchical regions displayed as
; part of a signal name shown in the waveform window.  The default
; value or a value of zero tells VSIM to display the full name.
; WaveSignalNameWidth = 0

; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1

; Turn off warnings from the IEEE numeric_std and numeric_bit
; packages.
; NumericStdNoWarnings = 1

; Control the format of a generate statement label. Don't quote it.
; GenerateFormat = %s__%d

; Specify whether checkpoint files should be compressed.
; The default is to be compressed.
; CheckpointCompressMode = 0

; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
; Warning -- Do not edit the project properties directly.
;            Property names are dynamic in nature and property
;            values have special syntax.  Changing property data directly
;            can result in a corrupt MPF file.  All project properties
;            can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 58
Project_File_0 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_32x24.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 39 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_256x32.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_top.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x22.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 41 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 49 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_iwb_biu.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 26 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_lsu.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_tlb.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_top.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 47 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_reg2mem.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 34 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rf.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 35 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x14.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 40 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mult_mac.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_fsm.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 50 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pm.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 32 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_tag.v
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Project_File_19 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cpu.v
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Project_File_21 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rfram_generic.v
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Project_File_22 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tpram_32x32.v
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Project_File_23 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_ram.v
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Project_File_24 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_freeze.v
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Project_File_25 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_gmultp2_32x32.v
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Project_File_26 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pic.v
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Project_File_27 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_genpc.v
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Project_File_28 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb.v
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Project_File_29 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wb_biu.v
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Project_File_30 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb_fifo.v
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Project_File_31 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
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Project_File_32 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_qmem_top.v
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Project_File_33 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x24.v
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Project_File_34 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_operandmuxes.v
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Project_File_35 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
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Project_File_36 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_if.v
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Project_File_37 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mem2reg.v
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Project_File_38 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tt.v
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Project_File_39 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_top.v
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Project_File_40 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_du.v
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Project_File_41 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_fsm.v
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Project_File_42 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_alu.v
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Project_File_43 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_top.v
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Project_File_44 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_128x32.v
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Project_File_45 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_512x20.v
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Project_File_46 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ctrl.v
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Project_File_47 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sprs.v
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Project_File_48 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v
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Project_File_49 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_tlb.v
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Project_File_50 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cfgr.v
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Project_File_51 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_tag.v
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Project_File_52 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_ram.v
Project_File_P_52 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_53 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wbmux.v
Project_File_P_53 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 57 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_54 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v
Project_File_P_54 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_55 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
Project_File_P_55 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 48 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_56 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_except.v
Project_File_P_56 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_57 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_256x21.v
Project_File_P_57 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 44 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick = 
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick = 
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick = 
PSL_DoubleClick = Edit
PSL_CustomDoubleClick = 
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick = 
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick = 
TCL_DoubleClick = Edit
TCL_CustomDoubleClick = 
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick = 
VCD_DoubleClick = Edit
VCD_CustomDoubleClick = 
SDF_DoubleClick = Edit
SDF_CustomDoubleClick = 
XML_DoubleClick = Edit
XML_CustomDoubleClick = 
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick = 
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick = 
Project_Major_Version = 6
Project_Minor_Version = 5