OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

Subversion Repositories or1200_soc

[/] [or1200_soc/] [trunk/] [boards/] [de1_board/] [libs/] [wb_size_bridge.cr.mti] - Rev 21

Go to most recent revision | Compare with Previous | Blame | View Log

C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module async_mem_if

Top level modules:
        async_mem_if

} {} {}} C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module asram_if

Top level modules:
        asram_if

} {} {}} C:/qaz/_CVS_WORK/units/wb_size_bridge/src/wb_size_bridge.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/wb_size_bridge.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module wb_size_bridge

Top level modules:
        wb_size_bridge

} {} {}}

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.