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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's ALU //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// ALU //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.7 2002/09/03 22:28:21 lampret // As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. // // Revision 1.6 2002/03/29 16:40:10 lampret // Added a directive to ignore signed division variables that are only used in simulation. // // Revision 1.5 2002/03/29 16:33:59 lampret // Added again just recently removed full_case directive // // Revision 1.4 2002/03/29 15:16:53 lampret // Some of the warnings fixed. // // Revision 1.3 2002/01/28 01:15:59 lampret // Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. // // Revision 1.2 2002/01/14 06:18:22 lampret // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. // // Revision 1.1 2002/01/03 08:16:15 lampret // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. // // Revision 1.10 2001/11/12 01:45:40 lampret // Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. // // Revision 1.9 2001/10/21 17:57:16 lampret // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. // // Revision 1.8 2001/10/19 23:28:45 lampret // Fixed some synthesis warnings. Configured with caches and MMUs. // // Revision 1.7 2001/10/14 13:12:09 lampret // MP3 version. // // Revision 1.1.1.1 2001/10/06 10:18:35 igorm // no message // // Revision 1.2 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "or1200_defines.v" module or1200_alu( a, b, mult_mac_result, macrc_op, alu_op, shrot_op, comp_op, result, flagforw, flag_we, cyforw, cy_we, carry ); parameter width = `OR1200_OPERAND_WIDTH; // // I/O // input [width-1:0] a; input [width-1:0] b; input [width-1:0] mult_mac_result; input macrc_op; input [`OR1200_ALUOP_WIDTH-1:0] alu_op; input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; input [`OR1200_COMPOP_WIDTH-1:0] comp_op; output [width-1:0] result; output flagforw; output flag_we; output cyforw; output cy_we; input carry; // // Internal wires and regs // reg [width-1:0] result; reg [width-1:0] shifted_rotated; reg flagforw; reg flagcomp; reg flag_we; reg cy_we; // synopsys translate_off `ifdef OR1200_SIM_ALU_DIV integer d1; integer d2; `endif // synopsys translate_on wire [width-1:0] comp_a; wire [width-1:0] comp_b; `ifdef OR1200_IMPL_ALU_COMP1 wire a_eq_b; wire a_lt_b; `endif wire [width-1:0] result_sum; `ifdef OR1200_IMPL_ADDC wire [width-1:0] result_csum; `endif wire [width-1:0] result_and; wire cyforw; // // Combinatorial logic // assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]}; assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]}; `ifdef OR1200_IMPL_ALU_COMP1 assign a_eq_b = (comp_a == comp_b); assign a_lt_b = (comp_a < comp_b); `endif assign {cyforw, result_sum} = a + b; `ifdef OR1200_IMPL_ADDC assign {cyforw, result_csum} = a + b + carry; `endif assign result_and = a & b; // // Simulation check for bad ALU behavior // `ifdef OR1200_WARNINGS // synopsys translate_off always @(result) begin if (result === 32'bx) $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time); end // synopsys translate_on `endif // // Central part of the ALU // always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin `ifdef OR1200_CASE_DEFAULT casex (alu_op) // synopsys parallel_case `else casex (alu_op) // synopsys full_case parallel_case `endif `OR1200_ALUOP_SHROT : begin result = shifted_rotated; end `OR1200_ALUOP_ADD : begin result = result_sum; end `ifdef OR1200_IMPL_ADDC `OR1200_ALUOP_ADDC : begin result = result_csum; end `endif `OR1200_ALUOP_SUB : begin result = a - b; end `OR1200_ALUOP_XOR : begin result = a ^ b; end `OR1200_ALUOP_OR : begin result = a | b; end `OR1200_ALUOP_IMM : begin result = b; end `OR1200_ALUOP_MOVHI : begin if (macrc_op) begin result = mult_mac_result; end else begin result = b << 16; end end `OR1200_ALUOP_MUL : begin result = mult_mac_result; `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result); // synopsys translate_on `endif end // synopsys translate_off `ifdef OR1200_SIM_ALU_DIV `OR1200_ALUOP_DIV : begin d1 = a; d2 = b; $display("DIV operation: %d / %d = %d", d1, d2, d1/d2); if (d2) result = d1 / d2; else result = 32'h00000000; end `endif `ifdef OR1200_SIM_ALU_DIVU `OR1200_ALUOP_DIVU : begin if (b) result = a / b; else result = 32'h00000000; end `endif // synopsys translate_on `ifdef OR1200_CASE_DEFAULT default: begin `else `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND `endif result = result_and; end endcase end // // Generate flag and flag write enable // always @(alu_op or result_sum or result_and or flagcomp) begin casex (alu_op) // synopsys parallel_case `ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS `OR1200_ALUOP_ADD : begin flagforw = (result_sum == 32'h0000_0000); flag_we = 1'b1; end `ifdef OR1200_IMPL_ADDC `OR1200_ALUOP_ADDC : begin flagforw = (result_csum == 32'h0000_0000); flag_we = 1'b1; end `endif `OR1200_ALUOP_AND: begin flagforw = (result_and == 32'h0000_0000); flag_we = 1'b1; end `endif `OR1200_ALUOP_COMP: begin flagforw = flagcomp; flag_we = 1'b1; end default: begin flagforw = 1'b0; flag_we = 1'b0; end endcase end // // Generate SR[CY] write enable // always @(alu_op) begin casex (alu_op) // synopsys parallel_case `ifdef OR1200_IMPL_ADDC `OR1200_ALUOP_ADDC : begin cy_we = 1'b1; end `endif default: begin cy_we = 1'b0; end endcase end // // Shifts and rotation // always @(shrot_op or a or b) begin case (shrot_op) // synopsys parallel_case `OR1200_SHROTOP_SLL : shifted_rotated = (a << b[4:0]); `OR1200_SHROTOP_SRL : shifted_rotated = (a >> b[4:0]); `ifdef OR1200_IMPL_ALU_ROTATE `OR1200_SHROTOP_ROR : shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]); `endif default: shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0]; endcase end // // First type of compare implementation // `ifdef OR1200_IMPL_ALU_COMP1 always @(comp_op or a_eq_b or a_lt_b) begin case(comp_op[2:0]) // synopsys parallel_case `OR1200_COP_SFEQ: flagcomp = a_eq_b; `OR1200_COP_SFNE: flagcomp = ~a_eq_b; `OR1200_COP_SFGT: flagcomp = ~(a_eq_b | a_lt_b); `OR1200_COP_SFGE: flagcomp = ~a_lt_b; `OR1200_COP_SFLT: flagcomp = a_lt_b; `OR1200_COP_SFLE: flagcomp = a_eq_b | a_lt_b; default: flagcomp = 1'b0; endcase end `endif // // Second type of compare implementation // `ifdef OR1200_IMPL_ALU_COMP2 always @(comp_op or comp_a or comp_b) begin case(comp_op[2:0]) // synopsys parallel_case `OR1200_COP_SFEQ: flagcomp = (comp_a == comp_b); `OR1200_COP_SFNE: flagcomp = (comp_a != comp_b); `OR1200_COP_SFGT: flagcomp = (comp_a > comp_b); `OR1200_COP_SFGE: flagcomp = (comp_a >= comp_b); `OR1200_COP_SFLT: flagcomp = (comp_a < comp_b); `OR1200_COP_SFLE: flagcomp = (comp_a <= comp_b); default: flagcomp = 1'b0; endcase end `endif endmodule
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