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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [bench/] [models/] [codec_model.v] - Rev 1765
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/////////////////////////////////////////////////////////////////// // Codec model for EK4520 // // The model simulated only mode that is found in Xess board which // is defined by: // CMODE = 0 // DIF0 = 0 // DIF1 = 1 // This mode represent MCLK = 256fs // 20 bit in/out MSB justified, SCLK = 64fs // // Functionality: // - The model takes the input channel and dumps the samples to // an output file. // - The model creates activity on the input channel according to // an input file. (not yet implemented) `include "timescale.v" module codec_model ( mclk, lrclk, sclk, sdin, sdout ); input mclk; input lrclk; input sclk; input sdin; output sdout; reg [19:0] left_data; reg [19:0] right_data; integer left_count, right_count; // The file descriptors integer left_file, right_file; assign sdout = 1'b0; // Opening the files for output data initial begin left_file = $fopen("../out/left.dat"); right_file = $fopen("../out/right.dat"); end // of opening files always @(negedge lrclk) begin left_count = 19; right_count = 19; $fdisplay(left_file, left_data); $fdisplay(right_file, right_data); end always @(negedge sclk) begin if ((left_count > 0) & (lrclk == 1'b0)) begin left_data[left_count] <= sdin; left_count <= left_count - 1; end if ((right_count > 0) & (lrclk == 1'b1)) begin right_data[right_count] <= sdin; right_count <= right_count - 1; end end endmodule