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[/] [or1k/] [branches/] [mp3_stable/] [mp3/] [bench/] [models/] [vga_model.v] - Rev 1765
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`include "timescale.v" module vga_model ( pclk, hsyncn, vsyncn, r,g,b ); input pclk; input hsyncn; input vsyncn; input [1:0] r; input [1:0] g; input [1:0] b; endmodule